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Staying Alert on the Road
Computer Vision and AI for Automotive Safety: Staying Alert on the Road … The future of the automotive experience is practically here … We’re not necessarily talking about automotive …
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SLAM and DSP Implementation
With the introduction of SLAM, there comes a need for more sophisticated DSPs to handle the required computations. To address this need, Cadence has introduced the Tensilica® Vision Q7 DSP.
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tensilica-vision-dsp-wp.pdf
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Tensilica Vision DSP Family
The Cadence® Tensilica® Vision digital signal processor (DSP) family—the Vision P5 DSP, and Vision P6 DSP—is designed for demanding imaging, computer vision, and neural network (NN) applications in the mob...
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Controller IP for Quad Serial-Peripheral Interface
Flash memory now utilized frequently in computers and electronic devices found in automotive, IoT, drones, connected home, and other emerging applications is demanding ever …
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Controller and PHY Automotive IP for Octal SPI Flash and HyperFlash
Flash memory storage is quickly expanding in Automotive, driven by Advanced Driver Assistance Systems (ADAS) and multimedia-rich Infotainment systems … The size of the SRAM is …
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Host Controller IP for xSPI
The Cadence® Denali® Gen2 High-Speed DDR PHY IP supports DDR 4/3L up to 3200Mbps.
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Controller and PHY IP for Octal SPI Flash
Flash memory is used frequently in computers and electronic devices found in Automotive, IoT, Drones, Connected Home, and other emerging applications, and is demanding ever …
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Cadence Leads Standards Activities at 3GPP and ITU-T to Enable Low-Power Implementations of Speech & Audio Codecs
Raj Pawate, Design Engineering Group Director at Cadence Design Systems, details the work done at Cadence focusing on 3GPP and ITU-T to Enable Low-Power Implementations of speech & Audio Codecs.
20 Apr 2021
Reviewing and Validating the Alternative EVS Codec
Hear from Stefan Dohla, Group Manager at Fraunhofer IIS, as he discusses the Alternative EVS Codec.
20 Apr 2021
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