Filter Results:
- System Design and Verification (201)
- Digital Design and Signoff (109)
- Custom IC - Analog - RF Design (92)
- PCB Design and Analysis (90)
- Innovus Implementation System (69)
- Tempus Timing Signoff Solution (55)
- Quantus QRC Extraction (47)
- Simulation and Testbench Verification (47)
- Silicon Signoff (44)
- Voltus IC Power Integrity Solution (40)
- Palladium XP Series (38)
- Virtuoso Layout Suite (35)
- Incisive Specman Elite (35)
- Acceleration and Emulation (34)
- Palladium Z1 Series (33)
- Genus Synthesis Solution (33)
- Virtuoso ADE Product Suite (29)
- Incisive Enterprise Simulator (29)
- Block Implementation (28)
- Protium FPGA-Based Prototyping Platform (27)
- IC Package Design and Analysis (27)
- Modus Test Solution (27)
- Flows SDV (24)
- FPGA-based Prototyping (24)
- Incisive vManager Solution (24)
- Allegro PCB Designer (22)
- JaperGold Verification Platform (22)
- Virtuoso ADE Assembler (21)
- Physical Verification System (21)
- Virtuoso Schematic Editor (21)
- Synthesis (21)
- SI PI Analysis (21)
- Library Characterization (21)
- Virtuoso Liberate MX (21)
- Virtuoso Liberate AMS (20)
- Liberate Trio Characterization Suite (20)
- Circuit Simulation (20)
- Voltus-Fi Custom Power Integrity Solution (20)
- Software-driven Verification (20)
- Virtuoso ADE Explorer (19)
- Virtuoso Liberate (19)
- Spectre Accelerated Parallel Simulator (19)
- Whiteboard Wednesdays (155)
- Tensilica Processor IP (122)
- Verification IP (83)
- Interface IP (82)
- Image Video Processing (54)
- Simulation VIP (42)
- HiFi Audio, Voice, Speech (38)
- Denali Memory IP (34)
- DDR IP (30)
- Accelerated VIP (27)
- USB IP (27)
- PCI Express IP (23)
- Memory Models (21)
- Fusion IoT DSP (21)
- MIPI IP (20)
Maxlinear Signing-Off using Tempus with Confidence for FinFET DesignsMaxlinear uses Tempus ECO and Tempus Signoff in an Innovus flow to reduce overall design closure time and achieve better PPA.
06 Apr 2020
|
Cadence Announces First Quarter 2020 Financial Results WebcastCadence to announce first quarter 2020 financial results via webcast with Lip-Bu Tan, Chief Executive Officer, and John Wall, Senior Vice President and Chief Financial Officer.
03 Apr 2020
|
Cadence Digital Full Flow Optimized to Deliver Improved Quality of Results with Up to 3X Faster ThroughputCadence announced that the new release of the Cadence digital full flow—proven with hundreds of completed advanced-node tapeouts—has been enhanced to further optimize power, performance and area (PPA) resu...
17 Mar 2020
|
Cadence Elects Ita Brennan and Lewis Chew to Board of DirectorsCadence announced the election of Ita Brennan and Lewis Chew to its board of directors, effective March 15, 2020.
16 Mar 2020
|
Tempus Power Integrity “True Signoff”Find silicon performance failures missed with normal IR analysis.
12 Mar 2020
|
Cadence Tensilica HiFi IP Accelerates AI Deployment with Support for TensorFlow Lite for MicrocontrollersCadence announced that software for Cadence Tensilica HiFi digital signal processors (DSPs) has been optimized to efficiently execute TensorFlow Lite for Microcontrollers, part of the TensorFlow end-to-end...
11 Mar 2020
|
tan.zip |
Intelligent System DesignLearn how Cadence’s Intelligent System Design strategy leverages computational software expertise so innovators are free to deliver groundbreaking products.
10 Mar 2020
|
cowie.zip |
devgan.zip |
|
Display:
|