Dynamic Duo 1
Dynamic Duo offers the most comprehensive solution for IP and SoC verification, HW/SW regressions, and early software Development
System emulation is the act of modeling the system environment to exercise a system under test that is designed to operate in that environment. In integrated circuit (IC) design, system emulation plays a significant role during the initial design phase of the chip to assure the register transfer level (RTL) representing the design is operating as expected in the system context. To achieve this, an emulator, usually a special-purpose-built computer hardware, is used to exercise and debug the design.
System emulation technology is used for debugging and functional verification to ensure the functionality of the logic. It can also verify the chip’s security, power, and safety. Usually, the model is built on the source code of hardware description languages and is compiled into the format used by the emulation system.
System emulation supports controllability and observability (the ability to trace multiple signals for many cycles). It provides internal values and allows you to stop execution for debugging. It also allows you to use an incomplete environment in an emulator, as you need not model the environment completely, therefore saving development cost and time. System emulation also helps to develop the software required for the chip during the design phase itself.
A physical device called an emulator is used for implementing system emulation. An emulator can map and place a chip into a virtual environment that imitates the actual environment for which it is designed.
An emulator has several blocks capable of taking a function, such as multiple field programmable gate arrays (FPGAs) and a programmable interconnect. This is required for an SoC with large blocks to be partitioned for verification.
The emulator also has a software toolchain that configures the interconnect within the chip to replace the design. It can also be connected to a testbench or used for co-emulation by connecting to another part of the circuit running in a logic simulator to accelerate the simulation.
Cadence® Palladium® emulation platforms provide early software development, hardware/software verification and debugging, and in-circuit emulation. They provide the highest debug productivity early in the design cycle when the RTL is still changing.
The Palladium Z2 system unifies best-in-class simulation acceleration and emulation technologies into a platform that is 2X more densely integrated and optimized for multi-user emulation throughput and efficiency.
It has advanced job re-shaping, relocation, and target relocation capabilities that allow you to manage system resources very efficiently for high utilization. Job parallelization is also available with the Palladium Z2 system due to its 8 million-gate job-size granularity. This enables you to run in parallel multiple simultaneous jobs, ranging from IP blocks to subsystem to system-level designs.