I Have a Digital Twin
In this episode of Chalk Talk, Amelia Dalton Chats with Cadence’s Frank Schirmeister about system-level optimization.
A digital twin is a virtual representation of a real-world entity or a system; in other words, a counterpart of a physical object or a process powered by technologies like machine learning (ML), the internet of things (IoT), and analytics. When developing expensive hardware or software like a cellphone, car, or fighter jet, a virtual model enables virtual collaboration, simulation, or data acquisition for better iterative design. It helps you understand the system’s performance and behavior in a real-world scenario. The virtual replication gives you the answers to the “what if” methods without breaking the prototype.
One of the main advantages of a digital twin is that the physical system and its digital twin can co-exist, communicate, and use real-life data from the physical system to improve the simulation. Digital twins are used across industries in several ways. For example, healthcare utilizes this capability for clinical diagnoses, learning, and training. Sectors such as automotive use the ability to optimize the manufacturing value chain, supply chain, product innovation, and enhancements.
Hardware-software partitioning in a parallel design cycle development environment accelerates design schedules. An integrated emulation and prototyping solution can maintain the design integrity that enables iterative and simultaneous verification, which can handle tasks of varied sizes and execution lengths, from smaller IP blocks to subsystems up to the SoC and system level. It is also essential to extend this verification effort across the enterprise to other designs being developed concurrently. When managing multiple SoC design projects, it is critical to have a platform that bridges the verification productivity gap to accelerate the verification of SoCs, subsystems, IP blocks, and system-level validation. And it is essential to take a holistic view of the parameters when evaluating emulation throughput.
Using a digital twin allows you to verify a chip and the software on that chip. The combined use of the Dynamic Duo emulation and prototyping platforms enables you to transition quickly and effortlessly from debugging a chip on the emulation platform to debugging the software running on that chip with the prototyping platform. Digital twins play a crucial role in redefining the emulation architecture with microprocessor-based technology.
On their own, Cadence’s Dynamic Duo of the Palladium and Protium platforms provide best-in-class emulation and FPGA prototyping; together, they unleash the true potential needed to develop products with digital twinning and differentiation. The Palladium platform has its core strength in SoC verification from custom IC and simulation bring-up to debug activity. The Protium platform has superior performance in fast pre-silicon software bring-up, software, and fast regression. Seamless transitions between the two engines are provided using Cadence flows and peripherals, including SpeedBridge adapters, accelerator verification IP (AVIP), and the memory model portfolio (MMP). With 2X capacity, rack improvements, and 1.5X performance, the Dynamic Duo 2.0 is the next-generation Palladium Z2/ Protium X2 emulation and prototyping platform to accelerate chip debug and pre-silicon software validation.