Luncheons

Luncheon Panels

We hosted luncheon sessions with lively debates on hot industry challenges.

Closing Analog and Mixed-Signal Verification in 5G, HPC, and Automotive

With 5G, high-performance computing, automotive, and other complex designs using images sensors, RFIC transceivers, and advanced nodes, verification across verticals poses the latest frontier of challenges looking for solutions. It is difficult to know when you are done with your electrical verification because 100% coverage is an evasive target and an acute problem for analog and AMS types of designs. Customers are routinely forced to make tradeoffs between time to market, functional coverage, reliability tests, accounting for statistical variance, etc. During the luncheon, attendees heard from industry luminaries who shared their solutions and plans to reach their verification goals.

Moderator:

• Prof. Georges Gielen, KU Leuven

Panelists:

• YY Chen, MediaTek
• Atul Bhargava, STMicroelectronics​
• Roopashree H M, Texas Instruments
• Vinod Kariat, Cadence

Machine Learning and Its Impact on the Digital Design Engineer

Much has been written, presented, and debated about machine learning and its potential impact on the future. Yet there is no debating that machine learning technology is already now inside production silicon that spans virtually every technology market segment. Today’s design engineer is at the forefront of this revolution.  During this panel, attendees had an opportunity to hear from engineers who are paving the next-generation chip design path. They discussed the lessons they’ve learned implementing these new classes of architectures and how our digital design, implementation, and signoff tools are evolving in lockstep using machine learning techniques to continue delivering optimal silicon.

Moderator:

• Prof. Andrew B. Kahng, UC San Diego

Panelists:

• Vishal Sarin, Analog Inference
• Andrew Bell, Groq
• Haoxing  Ren, NVIDIA
• Paul Penzes, Qualcomm
• Venkat Thanvantri, Cadence

Optimizing Verification Throughput for Advanced Designs in a Connected World

Verification throughput has become the key challenge for today’s and next-generation advanced SoCs to be successful in a connected world. Users must run as many cycles as possible in return for their tool and man-power investment, employing smart verification practices to correct as many bugs as early as possible per dollar and day. This panel discussed these challenges in the context of advanced 5G, AI/ML, ADAS, mobile, and server designs; introduced state-of-the-art, efficient techniques to increase and scale bare performance of dynamic verification engines; explored how to connect different levels of abstraction; and introduced smart bug-hunting techniques.

Moderator:

• Brian Bailey, Semiconductor Engineering

Panelists:

• Tran Nguyen, Arm
• Raju Kothandaraman, Intel
• Dale Chang, Samsung
• Paul Cunningham, Cadence

If you have any questions, email us at DAC2019@cadence.com