Cadence, our customers, and our partners shared their expertise and experiences in electronic design during our lunch panels.
If you have any questions, email us at DAC2017@cadence.com.
Towards Smarter Verification
Over the past decade, the core engines of functional verification have matured. Formal verification, simulation, emulation, and FPGA-based prototyping are the core anchors to deliver verification productivity. While they continue to evolve and differentiate on core parameters like performance, capacity, and memory footprint, the next leaps in productivity will be added in the fabric that binds them together with advanced analytics of the data created by the core engines. Smart switching between the engines to capitalize on their individual advantages, smart combination of engines to reap individual benefits, and advanced use models, flows, and methodologies combining the engines all will provide the next step function in productivity.
This panel reviewed the requirements for verification in an increasingly application-specific and connected world, and examined the key trends in verification productivity within both the core engines and verification fabric, including the trends for next-generation debug, machine-learning-based data analytics, automation of test-case creation, and continuous integration of hardware and software.
- Ann Mutschler, SemiEngineering
- Jim Hogan, Vista Ventures, LLC
- David Lacey, Hewlett Packard Enterprise
- Christopher Lawless, Intel
- Mike Stellfox, Cadence
High-Performance Digital Design at 7nm
Each new FinFET node and process comes with its own design rules and requirements for SoC engineers to manage—physics effects, lithography effects, and other process effects all add to the complexity. Designing at 7nm while simultaneously pushing power, performance, and area (PPA) requirements for new high-performance computing (HPC) and mobile platforms requires extensive industry collaboration. Our panel of industry experts discussed how to successfully take on these new requirements and benefit from the performance and efficiency improvements that 7nm offers.
The panel discussed the readiness of the process node, IP ecosystem, and Cadence digital flow for confidently supporting advanced 7nm design starts. Practical takeaways on how first-generation FinFET design knowledge can be leveraged to accelerate a transition to 7nm were explored, including new techniques such as via-pillar modeling, low-voltage optimization, clock mesh handling, and bus routing. Additionally, the panel took a closer look into what “reliability” now means at 7nm across the domains of electromigration, thermal, and packaging, and how designers should rethink when and how reliability is considered.
- Jim Hogan, Vista Ventures, LLC
- Robert Christy, ARM
- Tom Quan, TSMC
- Anand, Rajagopalan, MediaTek
- Kazuhiro Takahashi, Renesas
- Mitch Lowe, Cadence
Overcoming Mixed-Signal Design and Verification Challenges in Automotive and IoT Systems
The internet of things (IoT) is transforming our daily lives, particularly with the increasing popularity in connected cars over the past few years. As IoT devices in cars rely more and more on sensors for connectivity, methodologies to address and mitigate reliability challenges, as well as accurate reliability analysis, become mandatory to ensure that these devices continue to function correctly over time. In addition, miniaturization of IoT devices requires heterogeneous integration across chips of all process technologies down to 7nm, packages, and board. Our panel of industry luminaries shared their solutions and their plans to overcome design and verification challenges in the automotive and IoT world.
- Prof. Sayeef Salahuddin, UC Berkeley
- Pierluigi Daglio, STMicroelectronics
- Suresh Jayaraman, Amkor
- Goeran Jerke, Bosch
- Vinod Kariat, Cadence