Learn from Cadence Customers and Partners
As with previous years, the Cadence® Theater at DAC was a lively and popular place to learn, directly from our customers and partners, how to apply our technologies to real-world problems.
If you have any questions, email us at DAC2016@cadence.com.
Cadence Theater Presentations | |
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Design and Verification of Flexible 802.11ah Base Band IP Using High-Level Synthesis Adapt-IP |
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Emulation Productivity: Beyond the Specs AMD |
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Pre-silicon Software Development with Protium™/Palladium® Environments AMLogic |
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Full-Chip EMIR Analysis of Analog-on-Top Designs Using Voltus-Fi and Voltus Tools ams International AG |
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Accelerated System Optimization with CoreLink Creator and Interconnect Workbench ARM |
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Adoption of Genus RTL Synthesis Flow on Next-Generation ARM Processors ARM |
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How ARM and Cadence Partner to Accelerate IoT Design ARM |
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Kickstart Your IoT Design with Cadence and ARM
ARM |
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The ARM Universe of Models and its Interoperability with Cadence Verification Flows ARM |
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Accelerating Interface Debugging with Indago Protocol Debug App Cadence |
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Enabling First-Time Silicon Success with High-Performance DDR IP Cadence |
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USB Type-C - How Fast Will It Get to Market?
Cadence |
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Announcing Global Tensilica® Design Contest and How Cadence Supports Our University Software Program Members Cadence Academic Network |
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Managing AMS Designs for Successful Tapeouts ClioSoft |
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AMS Reference Flow for GLOBALFOUNDRIES 14nm FinFET Technology
GLOBALFOUNDRIES |
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Analog and Mixed-Signal Design with GLOBALFOUNDRIES 22FDX Technology GLOBALFOUNDRIES |
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FX-14 Tapeouts Using GLOBALFOUNDRIES ASIC Design Methodology GLOBALFOUNDRIES |
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Opening a New Dimension in Design with GLOBALFOUNDRIES 22FDX Technology GLOBALFOUNDRIES |
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Cadence and IMEC: Partnership to Make 5nm Design a Reality IMEC |
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IP Lifecycle Management - A Superior PLM Experience for Semiconductor Design Methodics |
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Exploiting SystemC-based Design and Xtensa® DSP Technology to Build ULP Wi-Fi HaLow™ MAC IP Methods2Business |
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MIPI® Alliance and IP: a Perspective for the Mobile and Mobile-Influenced Markets MIPI |
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Portable Stimulus for Verification and Post-Silicon Test – How to Connect These Two Worlds National Instruments |
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Tempus™ Concurrent Multi-mode, Multi-corner Analysis at NXP
NXP |
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Tempus Distributed STA at NXP
NXP |
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Next-Generation P&R Flow Setup with Innovus and 14nm Product Qualification
Samsung |
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Samsung Foundry Advanced FinFET Reference Flows with Tool Certifications for Multi-Core Designs
Samsung |
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Samsung Foundry 10nm Innovus Enablement and Qualification Samsung |
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Samsung Foundry 10nm Virtuoso Enablement and Qualification Samsung |
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Electrically Aware Design in SmartPower Technologies STMicroelectronics |
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Floorplan Management Using Smart Pin Group Guide Constraint In SmartPower Technologies
STMicroelectronics |
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Ultra-Low Voltage SRAM: Addressing the Characterization Challenge Surecore |
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Ubiquitous PCI Express Verification from Simulation Thru Post-Silicon Development Teledyne LeCroy |
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Power Grid Robustness Signoff at the Start of Physical Design Using Voltus™ Effective Resistance Analysis Texas Instruments |
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Scalable Synthesis: Initial Runtime and QoR Experiences Using Genus Solution
Texas Instruments |
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Writing Hierarchical SKILL PCells for Run-Time Performance and Memory Efficiency TowerJazz |
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Software-Driven Validation: Using Perspec System Verifier and DDGen Vayavya Labs |
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Announcing Global MEMS Design Contest X-FAB |
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Simplified design of low-RDS on drivers by using an advanced layout automation and verification flow
X-FAB |
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Cadence was excited to be a Platinum Sponsor with a prominent role at these premier technical event.
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