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    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Integrity 3D-IC Platform
          • Cadence Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Voltus IC Power Integrity Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
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          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • 112G/56G SerDes
          • Chiplet and D2D
          • Denali Memory Interface and Storage IP
          • Interface IP
          • PCIe and CXL
          • Tensilica Processor IP
        • RESOURCES
          • Discover PCIe
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
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          • Computational Fluid Dynamics
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  • Cadence Accelerates Industrial, Automotive, Hyperscale Data Center, and Mobile SoC Verification with Expanded VIP and System VIP Portfolio

Cadence Accelerates Industrial, Automotive, Hyperscale Data Center, and Mobile SoC Verification with Expanded VIP and System VIP Portfolio

01 Jun 2022

Latest additions enable comprehensive and fast verification to ensure SoCs meet the latest standard specifications

SAN JOSE, Calif.— Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced the availability of 15 new Verification IP (VIP) solutions that enable engineers to quickly and effectively verify their designs to meet the specifications for the latest standards protocols. The new Cadence® VIP offerings empower customers to confidently develop their next-generation industrial, automotive, hyperscale data center and mobile SoCs while keeping pace with the latest industry standards, including LPDDR5x, MIPI® CSI-2® 4.0 and UFS 4.0, and the newest versions of the USB4, Arm® AMBA® 5 CHI and GDDR interfaces.

The new Cadence VIP offer customers a comprehensive verification solution for the most complex protocols. Cadence customers have access to a consistent API across all VIP with complete bus function models (BFMs), integrated protocol checks and coverage models, facilitating rapid adoption. The VIP support multiple application areas and specifications, including:

  • Industrial:
    • MIPI I3Csm 1.1
    • MIPI CSI-2 4.0
    • eUSB2 1.2
  • Automotive:
    • MIPI A-PHYsm 1.0
    • MIPI DSI-2sm 2.0
    • Flash ONFI 5.0
    • CAN XL
  • Hyperscale data center:
    • CCIX 2.0
    • Latest version of AMBA CHI
    • Latest version of GDDR
  • Consumer and mobile:
    • DisplayPort 2.1
    • Ethernet 5G
    • LPDDR5x
    • Latest version of USB4
    • UFS 4.0

All Cadence VIP solutions include Cadence TripleCheck™ technology, which provides users with a specification-compliant verification plan linked to comprehensive coverage models and a test suite to ensure compliance with the interface specification. The new VIP also support the expanded Cadence System-Level Verification IP (System VIP), which provides SoC-level test libraries, performance analysis, and data and cache coherency checkers.

“STMicroelectronics has successfully utilized a broad range of Cadence VIP, including Arm AMBA, Memory Models, MIPI I3C and CSI-2, eUSB2 and the advanced Cadence System VIP solution, which enabled us to deliver industry-leading solutions for key projects, including ST Industrial MCUs and MPUs,” said Philippe d’Audigier, system-on-chip hardware design director at STMicroelectronics. “Cadence continues to deliver new VIP offerings and advanced SoC verification technologies that support the latest standards. We look forward to continuing our collaboration to develop our next-generation products.”

“As requirements evolve and demand increases for higher bandwidth, lower power and more effective cache coherency management, new protocols arrive to address these issues,” said Paul Cunningham, senior vice president and general manager of the System & Verification Group at Cadence. “By introducing these 15 new VIP, Cadence provides customers with solutions that ensure they can keep up with evolving standards. Our customers can confirm their designs comply with the standard specifications and application-specific timing, power and performance metrics, providing the fastest path to IP and SoC verification closure.”

The new VIP solutions are part of the broader Cadence verification full flow, which includes Palladium® Z2 emulation, Protium™ X2 prototyping, Xcelium™ simulation, the Jasper™ Formal Verification Platform, the Helium™ Virtual and Hybrid Studio and the vManager™ Verification Management Platform. The Cadence verification full flow delivers the highest verification throughput of bugs per dollar invested per day. The VIP solutions and verification full flow support the company’s Intelligent System Design™ strategy, enabling SoC design excellence. For more information, please visit www.cadence.com/go/NewVerificationIP.

About Cadence

Cadence is a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial and healthcare. For eight years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For. Learn more at cadence.com.

© 2022 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. Arm and AMBA are registered trademarks or trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. MIPI, A-PHY, CSI-2, DSI-2, and I3C are registered trademarks or service marks owned by MIPI Alliance. All other trademarks are the property of their respective owners.

Category: Featured

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Source: Cadence Design Systems, Inc.

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