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  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Integrity 3D-IC Platform
          • Cadence Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Voltus IC Power Integrity Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
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          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
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          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • 112G/56G SerDes
          • Chiplet and D2D
          • Denali Memory Interface and Storage IP
          • Interface IP
          • PCIe and CXL
          • Tensilica Processor IP
        • RESOURCES
          • Discover PCIe
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
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        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
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          • Signal and Power Integrity
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          • AWR Free Trial
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          • Augmented Reality Lab Tools
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  • 16 Nov 2021

Samsung Foundry Adopts Cadence Liberate Trio Characterization Suite for 3nm Production Library

SAN JOSE, Calif., 16 Nov 2021

Highlights:

  • Cadence characterization suite provided improved turnaround time, enabling Samsung Foundry to get to market faster
  • 3nm production libraries can be used across a variety of application areas

Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced Samsung Foundry successfully used the Liberate™ Trio Characterization Suite to deliver 3nm production libraries that meet the requirements for a range of application areas. The unified Cadence® library characterization system provided a powerful combination of characterization and library validation, enabling Samsung to reduce turnaround time and improve productivity versus previous nodes.

Ideal for the Samsung 3nm advanced-node technologies characterization, the Liberate Trio suite empowered the Samsung Foundry team to become much more efficient and speed time to market.

The Samsung team benefitted from the following key capabilities:

  • Advanced unified production-proven characterization flow: Combined nominal, statistical characterization and validation runs eliminated the need for Samsung to manage multiple runs, improving performance and overall efficiency.
  • Unified methodology for LVF generation: The next-level statistical characterization across multiple voltage profiles covered all corners adaptively and automatically and delivered an LVF format that captured process variations for the most advanced nodes, providing Samsung with significant runtime savings.
  • Latest generation multi-PVT flow: Samsung leveraged the latest integrated version of the Liberate characterization flow, where Liberate intelligently shared the circuit analysis results and generated collateral for SPICE simulation among multiple PVT corners , which further reduced overhead and runtime.
  • Machine learning (ML) capabilities: The ML algorithms enabled Samsung to reduce runtime on its most challenging cells while meeting accuracy criteria.
  • Scalable, reliable cloud-ready suite: Optimized for the cloud with robust job management, recovery and incremental run capabilities, the Liberate Trio suite allowed Samsung to scale their project to a large CPU farm, reducing the time needed to characterize large libraries.

“We selected the Liberate Trio Characterization suite for 3nm designs and above because it allowed us to meet our next-generation requirements, aggressive time-to-market windows and design enablement quality goals,” Sangyun Kim, vice president of the Design Technology Team at Samsung Electronics. “The suite provided our team with highly accurate characterization while significantly reducing our delivery timeline, hardware requirements and cost.”

“Cadence and Samsung Foundry have worked together on design enablement for many process generations, and it was a natural extension for the Samsung Foundry team to adopt the Liberate Trio Characterization suite to address all aspects of standard cell library characterization and validation,” said Michael Jackson, corporate vice president, R&D in the Digital & Signoff Group at Cadence. “Our latest design enablement collaboration enabled Samsung Foundry to benefit from the tightly integrated Cadence design flows and meet both time-to-market and quality goals for their most challenging libraries.”

The Liberate Trio Suite is part of the broader digital full flow, which supports the company’s Intelligent System Design™ strategy and enables SoC design excellence. For more information on the Liberate Trio Suite, please visit www.cadence.com/go/liberatetsuitepr.

About Cadence

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications, including consumer, hyperscale computing, 5G communications, automotive, mobile, aerospace, industrial and healthcare. For seven years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For. Learn more at cadence.com.

For more information, please contact:

Cadence Newsroom
408-944-7039
newsroom@cadence.com

© 2021 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.

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