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  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Integrity 3D-IC Platform
          • Cadence Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Voltus IC Power Integrity Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
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          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • 112G/56G SerDes
          • Chiplet and D2D
          • Denali Memory Interface and Storage IP
          • Interface IP
          • PCIe and CXL
          • Tensilica Processor IP
        • RESOURCES
          • Discover PCIe
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
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        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
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          • Clarity 3D Transient Solver
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          • AWR Free Trial
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          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
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          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
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  • 08 Apr 2021

Cadence Collaborates with Samsung Foundry to Accelerate Hyperscale Computing SoC Design for Process Nodes Down to 4nm

SAN JOSE, Calif., 08 Apr 2021

Highlights:

  • Cadence 20.1 digital full flow tuned for Samsung Foundry advanced-process nodes, enabling optimal PPA and first-pass silicon success
  • HPC reference flows based on iSpatial technology enable rapid design implementation
  • Digital flow’s ML and concurrent macro, standard cell and placement capabilities deliver improved productivity and design optimization

Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that it has optimized the Cadence® digital 20.1 full flow for Samsung Foundry’s advanced-process technologies down to 4nm. Through the collaboration, designers can use the Cadence tools to achieve optimal power, performance, and area (PPA) and deliver accurate, first-pass silicon for hyperscale computing applications.

The Cadence digital 20.1 flow provides capabilities that are well-suited for Samsung Foundry’s advanced-process technologies. For example, the iSpatial technology allows a seamless transition from the Genus™ Synthesis Solution to the Innovus™ Implementation System using a common user interface and database. Machine learning (ML) capabilities enable users to leverage their existing designs to train the GigaOpt™ optimization technology to minimize design margins versus traditional place-and-route flows.

Combined with a high-performance clock mesh architecture, the digital GigaPlace XL technology offers concurrent macro and standard cell placement that enables automated floorplanning, delivering better designer productivity and significantly improved wirelength and power. Unified implementation, timing and IR signoff engines enhance signoff convergence and reduce design margins and iterations. To speed the design process in Samsung Foundry’s advanced-process technologies, example flows are now provided for common high-performance computing (HPC) tasks such as concurrent macro and standard cell placement, clock mesh, balanced H Tree clock distribution, power delivery network and IR optimization.

The complete Cadence RTL-to-GDS flow optimized for Samsung Foundry process technologies includes the Genus Synthesis Solution, Cadence Modus DFT Software Solution, Innovus Implementation System, Quantus™ Extraction Solution, Tempus™ Timing Signoff Solution, Tempus ECO Option, Tempus Power Integrity Solution, Voltus™ IC Power Integrity Solution, Conformal® Equivalence Checker, Conformal Low Power, Litho Physical Analyzer and CMP Predictor.

“With the ongoing innovation in hyperscale computing and autonomous driving, there is ever-increasing demand for HPC capacity,” said Sangyun Kim, vice president of the Foundry Design Technology Team, at Samsung Electronics. “By combining the latest Samsung Foundry advanced-process nodes with the Cadence 20.1 digital full flow, our customers can achieve their design goals quickly and efficiently.”

“The newly optimized Cadence digital flow makes it much simpler for customers to achieve PPA targets using Samsung Foundry’s advanced-process technologies,” said Michael Jackson, corporate vice president, R&D in the Digital & Signoff Group at Cadence. “By expanding upon our longstanding collaboration with Samsung Foundry, designers can rapidly adopt Samsung Foundry’s validated HPC methodologies to deliver exceptional silicon performance on time.”

The Cadence 20.1 digital full flow supports the company’s Intelligent System Design™ strategy, enabling customers to achieve SoC design excellence. For more information on the digital design solutions for advanced nodes, please visit www.cadence.com/go/advnodes.

About Cadence

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications, including consumer, hyperscale computing, 5G communications, automotive, mobile, aerospace, industrial and healthcare. For six years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For. Learn more at cadence.com.

For more information, please contact:

Cadence Newsroom
408-944-7039
newsroom@cadence.com

© 2021 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.

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