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  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Integrity 3D-IC Platform
          • Cadence Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Voltus IC Power Integrity Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • 112G/56G SerDes
          • Chiplet and D2D
          • Denali Memory Interface and Storage IP
          • Interface IP
          • PCIe and CXL
          • Tensilica Processor IP
        • RESOURCES
          • Discover PCIe
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • Multiphysics System Analysis
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Fidelity CFD
          • Sigrity Advanced SI
          • Celsius Advanced PTI
          • RESOURCES
          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
      • Embedded Software
      • PCB Design and Analysis
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • Allegro X Design Platform
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  • 09 Dec 2019

Global Unichip Corporation Uses Cadence Digital Implementation and Signoff Flow to Deliver Advanced-Node Designs for AI and HPC Applications

Cadence Innovus Implementation System and Voltus IC Power Integrity Solution enable GUC to achieve first-pass silicon success and meet GHz performance target for multi-billion gate designs

SAN JOSE, Calif., 09 Dec 2019

Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that Global Unichip Corporation (GUC) successfully deployed the Cadence® digital implementation and signoff flow and delivered advanced-node (N16, N12 and N7) designs for artificial intelligence (AI) and high-performance computing (HPC) applications. Through use of the Cadence Innovus™ Implementation System and the Voltus™ IC Power Integrity Solution, GUC achieved first-pass silicon success and met its GHz performance target for its multi-billion gate designs. For more information on the Cadence digital and signoff flow, please visit www.cadence.com/go/dsfcspr.

Traditional digital implementation and signoff tools lack the capacity GUC required for their multi-billion gate designs during the implementation and signoff stages. Alternative solutions on the market must be greatly scripted because they don’t offer a shared data model-level integration, requiring more manual work with increased design margins and limited performance. Where the traditional tools fall short, the tightly integrated Cadence solution helped GUC meet power, performance and area (PPA) targets and deliver their large-capacity, advanced designs on time.

The Innovus Implementation System improved the GUC design team’s productivity through its efficient hierarchical partitioning flow, advanced top-level floorplanning and block implementation and closure capabilities. The Voltus IC Power Integrity Solution enabled GUC to accurately analyze the top-level full-chip static/dynamic power, IR drop and electro-migration through its distributed processing capability using innovative extensive parallelism technology. The seamless shared data model-level integration between the Cadence tools provides GUC with an efficient way to close signoff EM-IR issues during block implementation, reducing costly iterations and engineering change orders (ECOs).

“As a leader in ASIC design, we need to deliver highly complex designs to customers quickly, particularly for emerging application areas like AI and HPC,” said Louis Lin, senior vice president of Design Services at GUC. “Through our deep collaboration with Cadence, we deployed their digital implementation and signoff tools quickly and easily, and the Cadence team also provided prompt support to further optimize our delivery cycle time and achieve our PPA targets.”

The Cadence Innovus Implementation System and Voltus IC Power Integrity Solution are part of the broader digital implementation and signoff full flow and provide customers with a faster path to design closure. The tools in the flow support the company’s Intelligent System Design™ strategy, enabling advanced-node system-on-chip (SoC) design excellence for AI and HPC applications.

About Cadence

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and semiconductor IP are used by customers to deliver products to market faster. The company’s Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For. Learn more at www.cadence.com.

For more information, please contact:

Cadence Newsroom
408-944-7039
newsroom@cadence.com

© 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.

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