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  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Genus Synthesis Solution
          • Conformal Smart LEC
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Virtuoso RF Solution
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus IC Power Integrity Solution
          • RESOURCES
          • Flows
      • System Design and Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Emulation
          • Formal and Static Verification
          • FPGA-Based Prototyping
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • JasperGold Formal Verification Platform
          • Xcelium Logic Simulation
          • Palladium Z1 Enterprise Emulation Platform
          • Protium X1 Enterprise Prototyping Platform
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • Interface IP
          • Denali Memory IP
          • Tensilica Processor IP
          • Analog IP
          • System / Peripherals IP
          • Verification IP
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
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        • PRODUCT CATEGORIES
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Sigrity Advanced SI
          • Sigrity Advanced PI
          • RESOURCES
          • System Analysis Resources Hub
      • Embedded Software
      • PCB Design and Analysis
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          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
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          • RF / Microwave Design
          • Augmented Reality Lab Tools
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          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • RESOURCES
          • What's New in Allegro
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  • 16 July 2019

Cadence Delivers Portable Test and Stimulus Methodology and Library

SAN JOSE, Calif., 17 Jul 2019

Highlights:

  • Cadence delivers Portable Stimulus Methodology and Library: A Portable Test and Stimulus Specification-compliant source code form of the popular Perspec System Methodology Library and PSS methodology documentation
  • AMIQ confirms methodology and library code is compliant to Portable Test and Stimulus Specification standard using their DVT Eclipse Integrated Development Environment.

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced delivery of the Accellera Portable Test and Stimulus Specification (PSS) 1.0-compliant implementation of the popular Cadence® Perspec™ System Methodology Library (SML) and methodology documentation. This new PSS methodology and library was checked by AMIQ using their DVT Eclipse IDE to confirm the new library is PSS Language Reference Manual compliant.

The PSS methodology library enables Cadence Perspec System Verifier customers to access PSS source code for any of the SML functions to develop their models, saving them a minimum of eight weeks of development versus manual library creation. In addition, Cadence will also provide the library in source form along with the methodology documentation to non-Perspec users to help promote the adoption of the PSS. For more information on the Cadence Perspec System Verifier and the PSS methodology and library, please visit www.cadence.com/go/PSSMethodology.  

The PSS methodology document and library are accessible via download, providing customers with the flexibility of increased automation capabilities and platform portability. The methodology and library features include:

  • PSS model library: Users gain access to a compliant PSS model library for common processor actions and memory operations.
  • Guidelines for PSS model packaging and adoption: Users gain access to a directory and naming and packaging guidelines that make PSS-reusable code more consistent and easier to package and share.
  • Fully explained patterns and code examples for PSS modeling: Users have access to a dictionary of patterns that they can review and customize to solve their specific needs. Additionally, the patterns demonstrate PSS model reuse and extensibility, allowing platform portability and vertical reuse.

“Users appreciate the power of the latest standards for enabling industry progress and multi-vendor support,” said Cristian Amitroaie, CEO of AMIQ EDA. “We collaborated with Cadence using our DVT Eclipse IDE to provide a way to check the library for compliance to the standard. The combination of our IDE features and realistic examples helps users become familiar with PSS and develop compliant, vendor-neutral models for a variety of applications.”

“Delivering the PSS methodology and library exemplifies our commitment to facilitating further adoption of PSS to tackle complex verification challenges,” said Ziyad Hanna, corporate vice president, R&D in the System & Verification Group at Cadence. “Our focus is to continually reduce the cost of finding bugs, and the PSS is critical in this quest. By offering our library in PSS-compliant form, customers can design with confidence and speed time to market.”

The Perspec System Verifier improves system-level test productivity by up to 10X. It is part of the Cadence Verification Suite comprised of best-in-class core engines, verification fabric technologies and solutions that increase verification throughput. Together, they support the company’s Intelligent System Design™ strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently.

About Cadence

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and semiconductor IP are used by customers to deliver products to market faster. The company’s Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For. Learn more at cadence.com.

For more information, please contact:

Cadence Newsroom
408-944-7039
newsroom@cadence.com

© 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.

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For more information, please contact:

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newsroom@cadence.com

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