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  • Products

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      Cadence.AI

      • Millennium Platform

        AI-driven digital twin supercomputer

      • Cadence Cerebrus AI Studio

        Multi-block, multi-user SoC design platform

      • Optimality Intelligent System Explorer

        AI-driven Multiphysics analysis

      • Verisium Verification Platform

        AI-driven verification platform

      • Allegro X AI

        AI-driven PCB Design

      • Tensilica AI Platform

        On-device AI IP

    • Products

      IC Design & Verification

      • Virtuoso Studio

        Analog and custom IC design

      • Spectre Simulation

        Analog and mixed-signal SoC verification

      • Innovus+ Platform

        Synthesis and implementation for advanced nodes

      • Xcelium Logic Simulation

        IP and SoC design verification

      • Silicon Solutions

        Protocol IP and Compute IP, including Tensilica IP

      • Palladium and Protium

        Emulation and prototyping platforms

    • Products

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      • Allegro X Design Platform

        System and PCB design platform

      • Allegro X Adv Package Designer Platform

        IC packaging design and analysis platform

      • Sigrity X Platform

        Signal and power integrity analysis platform

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        RF and microwave development platform

      • Cadence Reality Digital Twin Platform

        Data center design and management platform

      • Fidelity CFD Platform

        Computational fluid dynamics platform

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  • 2019
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  • 25 Feb 2019

Cadence CMP Process Optimizer Enables Toshiba Memory Corporation to Accelerate Delivery of Advanced 3D Flash Memory Devices

Toshiba Memory Corporation achieves extremely high correlation to silicon with Cadence CMP Process Optimizer

SAN JOSE, Calif., 25 Feb 2019

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that Toshiba Memory Corporation has successfully used the Cadence® CMP Process Optimizer, a model calibration and prediction tool that accurately simulates multi-layer thickness and topography variability for the entire layer stack, to accelerate the delivery of its advanced 3D flash memory devices. With the Cadence solution in place, Toshiba Memory Corporation achieved 95.7 percent accuracy to silicon.

After conducting a thorough competitive evaluation, Toshiba Memory Corporation adopted the Cadence CMP Process Optimizer for its unparalleled feature set that addresses diverse layout topologies of array-based memory designs. The Cadence CMP Process Optimizer is based on a model-based approach versus a traditional, rules-based approach, which enabled Toshiba Memory Corporation to better predict complex, cumulative and long-range effects of chemical mechanical polishing (CMP) effects and CMP yield-limiting hotspots. Also, the Cadence CMP Process Optimizer allowed Toshiba Memory Corporation to perform simulations for the entire design stacks—both the transistor and routing layers—leading to improved accuracy. Toshiba Memory Corporation generated high-precision CMP models with the Cadence CMP Process Optimizer’s innovative capabilities. For more information on the Cadence CMP Process Optimizer, please visit www.cadence.com/go/ccpo.

“Advanced process technologies bring added complexities to the design process, and as a result, CMP effects have become more and more critical for us, particularly for our leading 3D flash memory solutions,” said Susumu Yoshikawa, technology executive, Memory Technology at Toshiba Memory Corporation. “We’ve been particularly impressed by the Cadence CMP Process Optimizer’s unparalleled capabilities, which enabled highly accurate modeling and analysis that we expect to improve product yield and accelerate the delivery of our flash devices.”

The Cadence CMP Process Optimizer offers feature-scale topography prediction and advanced reverse etch-back for accurate modeling and is part of the broader Cadence digital and signoff portfolio. From synthesis through implementation and signoff, the Cadence integrated full-flow digital and signoff tools provide a fast path to design closure and better predictability. The digital and signoff full-flow supports the company’s overall System Design Enablement strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently.

About Cadence

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and semiconductor IP are used by customers to deliver products to market faster. The company’s System Design Enablement strategy helps customers develop differentiated products—from chips to boards to systems—in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For. Learn more at www.cadence.com.

For more information, please contact:

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© 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.

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