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  • Products

    • Products

      Cadence.AI

      • Millennium Platform

        AI-driven digital twin supercomputer

      • Cadence Cerebrus AI Studio

        Multi-block, multi-user SoC design platform

      • Optimality Intelligent System Explorer

        AI-driven Multiphysics analysis

      • Verisium Verification Platform

        AI-driven verification platform

      • Allegro X AI

        AI-driven PCB Design

      • Tensilica AI Platform

        On-device AI IP

    • Products

      IC Design & Verification

      • Virtuoso Studio

        Analog and custom IC design

      • Spectre Simulation

        Analog and mixed-signal SoC verification

      • Innovus+ Platform

        Synthesis and implementation for advanced nodes

      • Xcelium Logic Simulation

        IP and SoC design verification

      • Silicon Solutions

        Protocol IP and Compute IP, including Tensilica IP

      • Palladium and Protium

        Emulation and prototyping platforms

    • Products

      System Design & Analysis

      • Allegro X Design Platform

        System and PCB design platform

      • Allegro X Adv Package Designer Platform

        IC packaging design and analysis platform

      • Sigrity X Platform

        Signal and power integrity analysis platform

      • AWR Design Environment Platform

        RF and microwave development platform

      • Cadence Reality Digital Twin Platform

        Data center design and management platform

      • Fidelity CFD Platform

        Computational fluid dynamics platform

    • All Analog IC Design Products
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  • 2019
  •   :  
  • 4 Mar 2019

Cadence Announces Complete, Silicon-Proven LPDDR5 IP Solution

Complete LPDDR5 IP Solution Includes Cadence PHY, Controller and Verification IP

SAN JOSE, Calif., 04 Mar 2019

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced early availability of the complete, silicon-proven Cadence® Denali® Gen2 IP for LPDDR5/4/4X in TSMC’s 7nm FinFET process technology. Offering up to 1.5X faster bandwidth than the fastest speed of LPDDR4 and LPDDR4X, the LPDDR5 standard enables high bandwidth with low power consumption, making it well suited for mobile computing, AI, IoT, cryptocurrency mining and automotive applications. The Cadence LPDDR5 IP solution consists of PHY, controller and Verification IP (VIP). For more information, please visit www.cadence.com/go/lpddr5ip.

Cadence’s first offering in the LPDDR5 design IP product line supports the pre-release LPDDR5 standard and LPDDR4/4X devices to allow maximum flexibility for end products with a range of performance/cost targets and long production runs. Because it is a single-vendor solution, the new Cadence LPDDR5 IP reduces integration challenges between the PHY, controller and the rest of the SoC. Cadence deploys proven design techniques that reuse technology from Cadence’s silicon-proven DDR designs, lowering customers’ risk when implementing LPDDR5 IP. The Cadence LPDDR5/4/4X controller is based on the industry-leading Denali DDR controller, and customers benefit from a full set of popular features for memory interfaces, such as support for Arm® AMBA® AXI buses and reliability features like in-line error correcting codes.

“Cadence’s demonstration of LPDDR5 design IP that is silicon proven in TSMC 7nm FinFET process technology enables many future chips that will embrace the LPDDR5 technology,” said Suk Lee, senior director of Design Infrastructure Management Division at TSMC. “TSMC’s 7nm process technology continues to be the 7nm process of choice for advanced designs, including mobile and automotive applications that LPDDR5 primarily focuses on.”

“Modern automotive and mobile applications require fast memory access to keep up with the rapid pace of industry innovation,” said Francisco Socal, senior product manager, Architecture and Technology Group at Arm. “The announcement of LPDDR5 design IP supporting AMBA protocols underscores our ongoing collaboration with Cadence and enables the ecosystem to deliver next-generation Arm-based processors uniquely designed for client and automotive applications.”

“Our LPDDR5 design IP in TSMC’s 7nm process technology is fully operational with available LPDDR5 modules,” said Amjad Qureshi, corporate vice president, R&D, design IP at Cadence. “Following our first-to-market LPDDR4, LPDDR4X, DDR5 and GDDR6 announcements, Cadence continues to execute on our strategy of being first to silicon with the most advanced memory technology interface IP. Cadence’s collaboration with leading DRAM providers enhances compatibility between customers’ SoCs and memory devices. Customers also benefit from Cadence’s single-vendor solution and silicon-proven design techniques leveraged through multiple generations of DDR/LPDDR designs, which together reduce customers’ interoperability risk and accelerate chip integration time.”

Availability

Cadence LPDDR5 IP is available now for customer engagements. Design files are ready for select customers to begin integration work with confidence that the Cadence LPDDR5 IP will work as intended in its application.

About Cadence

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and semiconductor IP are used by customers to deliver products to market faster. The company’s System Design Enablement strategy helps customers develop differentiated products—from chips to boards to systems—in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For. Learn more at www.cadence.com.

For more information, please contact:

Cadence Newsroom
408-944-7039
newsroom@cadence.com

© 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.

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