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  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Genus Synthesis Solution
          • Conformal Smart LEC
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Virtuoso RF Solution
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus IC Power Integrity Solution
          • RESOURCES
          • Flows
      • System Design and Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Emulation
          • Formal and Static Verification
          • FPGA-Based Prototyping
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • JasperGold Formal Verification Platform
          • Xcelium Logic Simulation
          • Palladium Z1 Enterprise Emulation Platform
          • Protium X1 Enterprise Prototyping Platform
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • Interface IP
          • Denali Memory IP
          • Tensilica Processor IP
          • Analog IP
          • System / Peripherals IP
          • Verification IP
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
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        • PRODUCT CATEGORIES
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Sigrity Advanced SI
          • Sigrity Advanced PI
          • RESOURCES
          • System Analysis Resources Hub
      • Embedded Software
      • PCB Design and Analysis
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • RESOURCES
          • What's New in Allegro
          • What's New in Sigrity
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      • AI IP Portfolio
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  • 2017
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  • 30 May 2017

New Cadence Virtuoso System Design Platform Provides Seamless Design Flow Between IC, Package and Board

Solution integrates the Virtuoso platform with Allegro and Sigrity technologies to streamline overall design process and significantly improve productivity and cycle time

SAN JOSE, Calif., 30 May 2017

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced the Cadence® Virtuoso® System Design Platform, a formal, streamlined and automated co-design and verification flow between the Cadence Virtuoso platform and Allegro® and Sigrity™ technologies. This higher level of integration enables engineers to design concurrently across the chip, package and board. By automating what has until now been a manual process, the Virtuoso System Design Platform minimizes errors and can reduce layout versus schematic (LVS) time between IC and package from days to minutes. For more information, visit www.cadence.com/go/virtuososdp.

Until now, advances in silicon technology have been sufficient for continued improvement in microelectronics products. Given the complexity of today’s chips, packages and boards, ICs based on both silicon and non-silicon materials are now required to design optimal high-performance systems. As a result, this trend is driving the need for engineers to integrate multiple heterogeneous technologies in a single product, affecting the performance and functionality of ICs and introducing a new set of challenges for semiconductor companies. To address these challenges, Cadence has developed a novel, cross-platform solution that streamlines and automates the design of a package or module featuring off-chip devices and multiple ICs based on differing process design kits (PDKs).

The Virtuoso System Design Platform allows IC designers to easily include system-level layout parasitics in the IC verification flow, enabling time savings by combining package/board layout connectivity data with the IC layout parasitic electrical model. The resulting automatically generated “system-aware” schematic can then be easily used to create a testbench for final circuit-level simulation. Until now, designers were only able to make changes after time-consuming manual checks involving spreadsheets and other ad hoc/manual methods, which can take days. By automating this entire flow, the Virtuoso System Design Platform eliminates the highly manual and error-prone process of integrating system-level layout parasitic models back into the IC designer’s flow, reducing days of work to mere minutes.

“We had been looking for a solution that created a tighter level of integration between our Virtuoso IC designers and our Allegro package design team,” said Toshihiko Himeno, group manager of the Design Methodology & Infrastructure Group at Toshiba Memory Corporation. “The new Cadence Virtuoso System Design Platform enables us to design a single hierarchical schematic to drive both IC and package layout while providing LVS checking, along with automating the library development process. We believe this new streamlined methodology will help to reduce our design-time cycles. Not only does the Virtuoso System Design Platform save us valuable time, but it eliminates what had until now been an error-prone process, giving us confidence that we’re taping out an accurate design.”

“With the increasing complexity of today’s chips, packages and boards, designing each in isolation is no longer feasible,” said Tom Beckley, senior vice president and general manager of the Custom IC & PCB Group at Cadence. “Cadence’s holistic, end-product focus from chips to packages to boards enables our customers to deliver the best possible systems and devices. With the Virtuoso System Design Platform, our customers can reduce risk and get to market faster with optimized designs featuring multiple heterogeneous ICs, including RF, analog and digital devices. This innovation is yet another result of Cadence’s System Design Enablement strategy.”

About Cadence

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and semiconductor IP are used by customers to deliver products to market faster. The company’s System Design Enablement strategy helps customers develop differentiated products—from chips to boards to systems—in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For. Learn more at www.cadence.com.

For more information, please contact:

Cadence Newsroom
408-944-7039
newsroom@cadence.com

© 2017 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.

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