Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its full-flow digital and signoff tools and its custom/analog tools have been certified/enabled for the Intel® 22FFL (FinFET Low-Power) process, which provides up to 100X lower leakage and a 2.5X active power reduction compared with its previous 22GP (general purpose) offering. Intel Custom Foundry utilized a PowerVR GT7200 graphics processing unit (GPU) from Imagination Technologies as part of the certification process.
The Cadence® flow, available to Intel Custom Foundry customers now, provides designers with optimal power, performance and area (PPA) for the creation of advanced-node mobile and embedded devices. To learn more about the Cadence full-flow digital and signoff solutions in the flow, visit www.cadence.com/go/intel22ffldands. For information about the Cadence custom/analog solutions in the flow, visit www.cadence.com/go/intel22fflcanda.
The tool certification and enablement provide Intel Custom Foundry customers with a complete and integrated system-on-chip (SoC) design flow. The following Cadence tools are included in the flow:
- Innovus™ Implementation System: This massively parallel physical implementation system utilizes GigaPlace™ placement technology, GigaOpt™ optimization technology and integrated color-/pin-access-/variability–aware routing and timing closure to deliver high-quality designs with competitive PPA targets while accelerating time to market.
- Genus™ Synthesis Solution: This RTL synthesis and physical synthesis engine mitigates productivity challenges faced by RTL designers, delivering up to 5X faster synthesis turnaround times and up to 20 percent datapath area reduction, while scaling linearly beyond 10M instances.
- Quantus™ QRC Extraction Solution: This solution uses a single Intel Custom Foundry-certified techfile and delivers a faster, scalable solution by supporting both cell-level and transistor-level extractions during design implementation and signoff with best-in-class accuracy versus foundry golden.
- Tempus™ Timing Signoff Solution: This massively parallelized timing signoff solution provides full-chip static timing analysis (STA) with gate-level delay calculation including signal integrity analysis, advanced on-chip variation analysis, advanced-node functionality required for double-patterning and waveform effects, and optimization for timing and leakage power.
- Voltus™ IC Power Integrity Solution: This cell-level power integrity solution supports comprehensive electromigration and IR drop (EM/IR) design rules and requirements while providing full-chip SoC power signoff accuracy.
- Voltus-Fi Custom Power Integrity Solution: This transistor-level power integrity solution supports comprehensive EM/IR design rules and requirements while providing SPICE-level power signoff accuracy for analog, memory and custom digital IP blocks.
- Physical Verification System: This system includes advanced technologies and rule decks to support design rule checks (DRCs), layout versus schematic (LVS), advanced metal fill, yield-scoring, voltage-dependent checks and in-design signoff.
- Virtuoso® Analog Design Environment (ADE) Product Suite: The suite enables engineers to fully explore, analyze and verify designs, ensuring that design quality is fully optimized within compressed design cycles.
- Virtuoso Layout Suite: The suite supports custom/analog, digital, and mixed-signal designs at the device, cell, block and chip levels, offering accelerated performance and productivity.
- Spectre® Classic Simulator, Spectre Accelerated Parallel Simulator (APS) and Spectre RF Simulation: These products deliver fast and accurate circuit simulation of complex analog, radio frequency (RF) and mixed-signal circuits with full support for advanced-node device models and parasitics.
Intel’s new 22FFL process delivers transistor drive currents on par with Intel’s 14nm technology. It has single patterned interconnects and simplified design rules for ease of use. For more information, please contact Intel Custom Foundry.
“Since 2011, Intel has delivered over 7 million FinFET wafers, and the new 22FFL process leverages all of that manufacturing experience to create a differentiating design platform for next generation IoT and entry mobile products,” said Dr. Changhong Dai, vice president, Technology and Manufacturing Group, and director, Technology Optimization Solutions at Intel Custom Foundry. “Intel Custom Foundry has worked closely with Cadence to deliver a complete design ecosystem for our customers who are creating innovative FinFET designs. The certified Cadence digital and signoff tools and custom/analog tools combined with the comprehensive Intel Custom Foundry 22FFL platform offer our mutual customers a complete and integrated flow to help them achieve optimal PPA on Intel’s 22FFL process technology.”
Mark Dickinson, executive vice president, PowerVR, Imagination Technologies, said, “Our PowerVR XT family of GPUs is designed to enable advanced graphics and efficient GPU compute performance for a wide range of mobile and embedded devices. The collaboration with Intel Custom Foundry and Cadence has enabled us to ensure the Cadence design flow provides great efficiencies on the new Intel Custom Foundry 22FFL process.”
“Our collaboration on the certification process provides customers with added confidence that they can overcome design complexities using the Cadence flow on Intel Custom Foundry's 22FFL design platform,” said KT Moore, vice president, product management in the Digital & Signoff Group at Cadence. “Intel Custom Foundry customers can now create differentiated SoCs on the new Intel 22FFL process using trusted, certified Cadence tools that can enable designers to deliver products to market faster."
