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  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Integrity 3D-IC Platform
          • Cadence Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Voltus IC Power Integrity Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • 112G/56G SerDes
          • Chiplet and D2D
          • Denali Memory Interface and Storage IP
          • Interface IP
          • PCIe and CXL
          • Tensilica Processor IP
        • RESOURCES
          • Discover PCIe
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • Multiphysics System Analysis
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
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          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Fidelity CFD
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          • Celsius Advanced PTI
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          • System Analysis Resources Hub
          • AWR Free Trial
      • Embedded Software
      • PCB Design and Analysis
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • Allegro X Design Platform
          • RESOURCES
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  • 24 May 2017

Cadence Digital, Signoff and Custom/Analog Tools Enabled on Samsung’s 7LPP and 8LPP Process Technologies

SAN JOSE, Calif., 24 May 2017

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its digital, signoff and custom/analog tools are enabled on Samsung Electronics’ 7LPP and 8LPP process technologies. The 7LPP and 8LPP process technologies continue to deliver power, performance and area optimizations with additional scaling benefits over previous generations of advanced FinFET nodes, and customers can begin working on early designs using these next-generation technologies.

The Cadence custom/analog, digital and signoff tools meet Samsung’s requirements, which can enable foundry customers to create complex, advanced-node mobile and other vertical market designs using Samsung’s 7LPP and 8LPP process technologies. To learn more about the Cadence® digital and signoff solutions, visit www.cadence.com/go/samsung7nm8nmdands. For information about the Cadence custom/analog solutions, visit www.cadence.com/go/samsung7nm8nmcanda.

The digital and signoff tools currently enabled on the Samsung 7LPP process include the Innovus™ Implementation System and Physical Verification System for DRC. The custom/analog tools enabled on the Samsung 7LPP process include the Virtuoso® Advanced-Node Platform, which consists of the Spectre® Accelerated Parallel Simulator (APS), the Spectre Extensive Partitioning Simulator (XPS), the Virtuoso ADE Product Suite, the Virtuoso Layout Suite, and the Virtuoso Schematic Editor. The Quantus™ QRC Extraction Solution and Physical Verification System for Layout Versus Schematic (LVS) and Manufacturability and Variability Solutions (MVS) are expected to be enabled on the 7nm LPP process by the end of June 2017.

The digital and signoff tools currently enabled on the Samsung 8LPP process include the Innovus Implementation System, Quantus QRC Extraction Solution and Physical Verification System. The custom/analog tools enabled on the Samsung 8LPP process include the Virtuoso Advanced-Node Platform, which consists of the Spectre Accelerated Parallel Simulator (APS), Spectre Extensive Partitioning Simulator (XPS), the Virtuoso ADE Product Suite, the Virtuoso Layout Suite, and the Virtuoso Schematic Editor.

“We’ve worked closely with Cadence to ensure that its custom/analog, digital and signoff tools enable customers to quickly and easily experience the benefits of our advanced-node process technologies,” said Jaehong Park, senior vice president of the Foundry Design Team at Samsung Electronics. “Enabling tools early is essential for our customers to deliver designs to their high-volume customers within tight market windows.”

“The Cadence tools that are enabled allow customers to achieve optimized power, performance and area results and remain competitive within their respective markets,” said Dr. Anirudh Devgan, executive vice president and general manager of the Digital & Signoff Group and the System & Verification Group at Cadence. “The close collaboration and efficient working model between Cadence and Samsung Foundry provides customers with confidence that these complex, advanced-node FinFET designs can be implemented quickly.”

About Cadence

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and semiconductor IP are used by customers to deliver products to market faster. The company’s System Design Enablement strategy helps customers develop differentiated products—from chips to boards to systems—in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For. Learn more at www.cadence.com.

For more information, please contact:

Cadence Newsroom
408-944-7039
newsroom@cadence.com

© 2017 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.

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