Highlights:
- Cadence tools optimized for mobile and HPC platforms
- Cadence achieves certification for custom/analog and digital tool suites for TSMC’s 7nm FinFET Plus process and adds new capabilities in support of both the 7nm FinFET Plus and 7nm process technologies
- Cadence library characterization tool flow supports 7nm FinFET Plus and 7nm processes
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced its collaboration with TSMC to advance 7nm FinFET Plus design innovation for mobile and high-performance computing (HPC) platforms. The Cadence® digital, signoff and custom/analog tools have achieved certification for the latest version of TSMC’s 7nm FinFET Plus process, and Cadence also delivered enhancements to the Cadence library characterization flow.
To learn more about the Cadence full-flow digital and signoff advanced-node solutions, visit www.cadence.com/go/tsmcadvnodedands. For information about the Cadence custom/analog advanced-node solutions, visit www.cadence.com/go/tsmcadvnodecanda.
New 7nm FinFET Plus Tool Certification and 7nm Flow Enhancements
Cadence digital implementation and signoff tools have been certified by TSMC for both the 7nm FinFET Plus and 7nm processes, and process design kits (PDKs) are immediately available for download. The digital implementation and signoff flow includes the Innovus™ Implementation System, Quantus™ QRC Extraction Solution, Tempus™ Timing Signoff Solution, Voltus™ IC Power Integrity Solution, Voltus-Fi Custom Power Integrity Solution, Physical Verification System (PVS) and Layout-Dependent Effect (LDE) Electrical Analyzer. Tool capabilities specifically designed for the 7nm FinFET Plus process include EUV layer support and expanded via-pillar support. Digital and signoff flow enhancements for the 7nm process include congestion and IR-driven placement, improved clock buffer clustering/placement/routing, and engine improvement in the NanoRoute™ tool for runtime and design rule check (DRC) quality.
The custom/analog tools certified for both the 7nm FinFET Plus and 7nm process include the Spectre® Accelerated Parallel Simulator (APS), Spectre eXtensive Partitioning Simulator (XPS), Spectre RF and Spectre Classic Simulator, as well as the Virtuoso® product suite, which consists of the Virtuoso Layout Suite, Virtuoso Schematic Editor and the Virtuoso Analog Design Environment (ADE). The tools offer advanced device snapping and an accelerated custom placement and routing flow, which enable customers to improve productivity and meet their power, multiple patterning, density and electromigration (EM) requirements.
By enhancing design methodologies and leveraging new capabilities within the Virtuoso Advanced-Node Platform, customers can achieve an improvement in custom physical design throughput versus traditional non-structured design methodologies when designing using the 7nm FinFET Plus and 7nm process technologies. Early customers have been able to maintain similar cycle times to the 16nm process by using the tool’s advanced-node capabilities like multi-patterning and color-aware layout, module generator (ModGen) device arrays, automated FinFET placement and variation analysis.
7nm FinFET Plus Library Characterization Tool Flow Delivery
In addition to the tools certified for TSMC's 7nm FinFET Plus and 7nm process technologies, the Virtuoso Liberate™ Characterization Solution and the Virtuoso Variety™ Statistical Characterization Solution have been validated to deliver accurate Liberty libraries including advanced timing, noise and power models for the 7nm FinFET Plus process. The solutions utilize innovative methods to characterize Liberty Variation Format (LVF) models, enabling accurate process variation signoff for low-voltage applications and creating EM models that enable signal EM optimizations and signoff.
“Working closely with TSMC on 7nm FinFET Plus and 7nm process technologies has enabled us to deliver best-in-class solutions to our advanced-node customers,” said Dr. Anirudh Devgan, executive vice president and general manager of the Digital & Signoff Group and the System & Verification Group at Cadence. “The latest certifications of our EDA tools have allowed us to aggressively target the growing number of advanced-node production designs in the mobile and high-performance computing markets, and customers can readily adopt our technologies to create high-quality, innovative designs today.”
“Our advanced-node customers have demonstrated success with designing and taping out complex SoCs using our 7nm process technology, and we’re seeing early adopters use our 7nm FinFET Plus process technology as well,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “Our strong partnership with Cadence through certification of their tools and flows for 7nm and 7nm FinFET Plus designs enables our customers to confidently achieve their design goals within a fast, predictable timeline.”
