Home
  • PRODUCTS
  • SOLUTIONS
  • SUPPORT
  • COMPANY
  • EN US
    • SELECT YOUR COUNTRY OR REGION

    • China - 简体中文
    • Japan - 日本語
    • Korea - 한국어
    • Taiwan - 繁體中文

DESIGN EXCELLENCE

  • Digital Design and Signoff
  • Custom IC
  • Verification
  • IP
  • IC Package

SYSTEM INNOVATION

  • System Analysis
  • Embedded Software
  • PCB Design

PERVASIVE INTELLIGENCE

  • AI / Machine Learning
  • AI IP Portfolio

CADENCE CLOUD

Digital Design and Signoff

Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

  • Logic Equivalence Checking
  • Innovus Implementation and Floorplanning
  • Functional ECO
  • Low-Power Validation
  • Synthesis
  • Power Analysis
  • Constraints and CDC Signoff
  • Silicon Signoff and Verification
  • Library Characterization
  • Test
  • Flows
  • Achieve best PPA with the next-generation Digital Full Flow solution Learn More
  • Address digital implementation challenges with machine learning Watch Now

Custom IC / Analog / RF Design

Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.

  • Circuit Design
  • Circuit Simulation
  • Layout Design
  • Layout Verification
  • Library Characterization
  • RF / Microwave Solutions
  • Flows
  • Solve analog simulation challenges in complex designs Watch Now
  • See how the Virtuoso Design Platform addresses advanced custom IC and system design challenges Watch Now

System Design and Verification

Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.

  • Debug Analysis
  • Emulation
  • Formal and Static Verification
  • FPGA-Based Prototyping
  • Planning and Management
  • Simulation
  • Software-Driven Verification
  • Verification IP
  • System-Level Verification IP
  • Flows
  • Prototype your embedded software development Watch Now
  • Learn how early firmware development enabled first silicon success at Toshiba Memory Watch Now

IP

An open IP platform for you to customize your app-driven SoC design.

  • Interface IP
  • Denali Memory IP
  • Tensilica Processor IP
  • Analog IP
  • System / Peripherals IP
  • Verification IP
  • Solve the challenges of long-reach signaling with Cadence 112G SerDes IP Watch Now
  • Meeting the needs of 5G communication with Tensilica® ConnX B20 DSP IP Download Now

IC Package Design and Analysis

Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.

  • Cross-Platform Co-Design and Analysis
  • IC Package Design
  • SI/PI Analysis
  • SI/PI Analysis Point Tools
  • Flows
  • Cadence Design Solutions certified for TSMC SoIC advanced 3D chip stacking technology Learn More
  • Four reasons to avoid multi-layer flip-chip pin padstacks Learn More

System Analysis

Cadence® system analysis solutions provide highly accurate electromagnetic extraction and simulation analysis to ensure your system works under wide-ranging operating conditions.

  • See how to improve electrical-thermal co-simulation with the Celsius™ Thermal Solver Watch Now
  • Get true 3D system analysis with faster speeds, more capacity, and integration Watch Now
  • Electromagnetic Solutions
  • RF / Microwave Design
  • Thermal Solutions
  • System Analysis Resources Hub

Embedded Software

PCB Design and Analysis

Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.

  • Design Authoring
  • PCB Layout
  • Library and Design Data Management
  • Analog/Mixed-Signal Simulation
  • SI/PI Analysis
  • SI/PI Analysis Point Tools
  • What's New in Allegro
  • What's New in Sigrity
  • RF / Microwave Design
  • Flows
  • Advanced PCB Design & Analysis Blog
  • Watch how to easily tackle complex and cutting edge designs. Learn More
  • Learn why signal integrity analysis needs to be power-aware Watch Now
  • Augmented Reality Lab Tools

AI / Machine Learning

AI IP Portfolio

INDUSTRIES

  • 5G Systems and Subsystems
  • Aerospace and Defense
  • Automotive
  • AI / Machine Learning

TECHNOLOGIES

  • 3D-IC Design
  • Advanced Node
  • Arm-Based Solutions
  • Cloud Solutions
  • Low Power
  • Mixed Signal
  • Photonics
  • RF / Microwave
See how our customers create innovative products with Cadence Explore Now

SUPPORT

  • Support Process
  • Online Support
  • Software Downloads
  • Computing Platform Support
  • Customer Support Contacts
  • Technical Forums

TRAINING

  • Custom IC / Analog / RF Design
  • Languages and Methodologies
  • Digital Design and Signoff
  • IC Package
  • PCB Design
  • System Design and Verification
  • Tensilica Processor IP
Stay up to date with the latest software Download Now
24/7 - Cadence Online Support Visit Now

CORPORATE

  • About Us
  • Designed with Cadence
  • Investor Relations
  • Leadership Team
  • Computational Software
  • Alliances
  • Corporate Social Responsibility
  • Cadence Academic Network

MEDIA CENTER

  • Events
  • Newsroom
  • Blogs

CULTURE AND CAREERS

  • Culture and Diversity
  • Careers
Learn how Intelligent System Design™ powers future technologies Learn More
Browse Cadence’s latest on-demand sessions and upcoming events. Explore More
View all Products
  • PRODUCTS
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • Logic Equivalence Checking
        • Innovus Implementation and Floorplanning
        • Functional ECO
        • Low-Power Validation
        • Synthesis
        • Power Analysis
        • Constraints and CDC Signoff
        • Silicon Signoff and Verification
        • Library Characterization
        • Test
        • Flows
      • Custom IC / Analog / RF Design
        • Circuit Design
        • Circuit Simulation
        • Layout Design
        • Layout Verification
        • Library Characterization
        • RF / Microwave Solutions
        • Flows
      • System Design and Verification
        • Debug Analysis
        • Emulation
        • Formal and Static Verification
        • FPGA-Based Prototyping
        • Planning and Management
        • Simulation
        • Software-Driven Verification
        • Verification IP
        • System-Level Verification IP
        • Flows
      • IP
        • Interface IP
        • Denali Memory IP
        • Tensilica Processor IP
        • Analog IP
        • System / Peripherals IP
        • Verification IP
      • IC Package Design and Analysis
        • Cross-Platform Co-Design and Analysis
        • IC Package Design
        • SI/PI Analysis
        • SI/PI Analysis Point Tools
        • Flows
    • SYSTEM INNOVATION
      • System Analysis
        • Electromagnetic Solutions
        • RF / Microwave Design
        • Thermal Solutions
        • System Analysis Resources Hub
      • Embedded Software
      • PCB Design and Analysis
        • Design Authoring
        • PCB Layout
        • Library and Design Data Management
        • Analog/Mixed-Signal Simulation
        • SI/PI Analysis
        • SI/PI Analysis Point Tools
        • What's New in Allegro
        • What's New in Sigrity
        • RF / Microwave Design
        • Flows
        • Advanced PCB Design & Analysis Blog
        • Augmented Reality Lab Tools
    • PERVASIVE INTELLIGENCE
      • AI / Machine Learning
      • AI IP Portfolio
    • CADENCE CLOUD
  • SOLUTIONS
      • INDUSTRIES
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • TECHNOLOGIES
        • 3D-IC Design
        • Advanced Node
        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • INDUSTRIES
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • TECHNOLOGIES
        • 3D-IC Design
        • Advanced Node
        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • INDUSTRIES
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • TECHNOLOGIES
        • 3D-IC Design
        • Advanced Node
        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • INDUSTRIES
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • TECHNOLOGIES
        • 3D-IC Design
        • Advanced Node
        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
  • SUPPORT
      • SUPPORT
        • Support Process
        • Online Support
        • Software Downloads
        • Computing Platform Support
        • Customer Support Contacts
        • Technical Forums
      • TRAINING
        • Custom IC / Analog / RF Design
        • Languages and Methodologies
        • Digital Design and Signoff
        • IC Package
        • PCB Design
        • System Design and Verification
        • Tensilica Processor IP
      • SUPPORT
        • Support Process
        • Online Support
        • Software Downloads
        • Computing Platform Support
        • Customer Support Contacts
        • Technical Forums
      • TRAINING
        • Custom IC / Analog / RF Design
        • Languages and Methodologies
        • Digital Design and Signoff
        • IC Package
        • PCB Design
        • System Design and Verification
        • Tensilica Processor IP
      • SUPPORT
        • Support Process
        • Online Support
        • Software Downloads
        • Computing Platform Support
        • Customer Support Contacts
        • Technical Forums
      • TRAINING
        • Custom IC / Analog / RF Design
        • Languages and Methodologies
        • Digital Design and Signoff
        • IC Package
        • PCB Design
        • System Design and Verification
        • Tensilica Processor IP
      • SUPPORT
        • Support Process
        • Online Support
        • Software Downloads
        • Computing Platform Support
        • Customer Support Contacts
        • Technical Forums
      • TRAINING
        • Custom IC / Analog / RF Design
        • Languages and Methodologies
        • Digital Design and Signoff
        • IC Package
        • PCB Design
        • System Design and Verification
        • Tensilica Processor IP
  • COMPANY
      • CORPORATE
        • About Us
        • Designed with Cadence
        • Investor Relations
        • Leadership Team
        • Computational Software
        • Alliances
        • Corporate Social Responsibility
        • Cadence Academic Network
      • MEDIA CENTER
        • Events
        • Newsroom
        • Blogs
      • CULTURE AND CAREERS
        • Culture and Diversity
        • Careers
      • CORPORATE
        • About Us
        • Designed with Cadence
        • Investor Relations
        • Leadership Team
        • Computational Software
        • Alliances
        • Corporate Social Responsibility
        • Cadence Academic Network
      • MEDIA CENTER
        • Events
        • Newsroom
        • Blogs
      • CULTURE AND CAREERS
        • Culture and Diversity
        • Careers
      • CORPORATE
        • About Us
        • Designed with Cadence
        • Investor Relations
        • Leadership Team
        • Computational Software
        • Alliances
        • Corporate Social Responsibility
        • Cadence Academic Network
      • MEDIA CENTER
        • Events
        • Newsroom
        • Blogs
      • CULTURE AND CAREERS
        • Culture and Diversity
        • Careers
      • CORPORATE
        • About Us
        • Designed with Cadence
        • Investor Relations
        • Leadership Team
        • Computational Software
        • Alliances
        • Corporate Social Responsibility
        • Cadence Academic Network
      • MEDIA CENTER
        • Events
        • Newsroom
        • Blogs
      • CULTURE AND CAREERS
        • Culture and Diversity
        • Careers

  • Home
  •   :  
  • About Us
  •   :  
  • Newsroom
  •   :  
  • News Releases
  •   :  
  • 24 Oct 2016

Cadence Reference Flow with Digital and Signoff Tools Certified on Samsung’s 10nm Process Technology

Reference flow enables system and semiconductor companies to accelerate delivery of designs on Samsung’s second-generation 10nm process (10LPP)

SAN JOSE, Calif., 24 Oct 2016

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its complete suite of digital and signoff tools has been certified for Samsung Electronics’ Process Design Kit (PDK) and Foundation Library on Samsung’s second-generation of 10nm LPP (Low Power Plus) process. Samsung also validated the Cadence® reference flow using a quad-core design with the ARM® Cortex®-A53 processor on the 10LPP process, which was implemented with the low-power design methodology covering power-gating and memory retention, IEEE 1801 UPF2.1 power intent, and statistical on-chip variation (SOCV)-based timing closure using the Liberty Variation Format (LVF) library.

The Cadence digital and signoff tools met all of Samsung’s accuracy requirements, enabling foundry customers to quickly achieve design closure and deliver large, complex FinFET designs faster with the 10LPP process. In addition, the Cadence signoff tools have been certified for tapeout using Samsung’s certification criteria for baseline accuracy. The tools in the design flow include:

  • Innovus™ Implementation System: Based on a massively parallel architecture, it enables larger designs and reduced turnaround time while supporting Samsung’s 10LPP design requirements, such as floorplanning, placement and routing with integrated color-/pin-access /variability-aware timing closure, and clock tree and power optimization
  • Genus™ Synthesis Solution: Delivers improved productivity during register-transfer level (RTL) design and highly correlated, optimal quality of results (QoR) in final implementation
  • Quantus™ QRC Extraction Solution: Offers best-in-class accuracy versus foundry baseline; faster, scalable cell-level and transistor-level extraction; multi-patterning; multi-coloring; and a built-in 3D extraction capability, Quantus Field Solver (FS)
  • Conformal® Logic Equivalence Checking (LEC): Ensures the correctness of logic changes and engineering change orders (ECOs) as well as the implementation flow, while enabling the comparison of different views/abstraction levels
  • Conformal Low Power: Enables the creation and validation of power intent in context of the design, combining low-power equivalence checking with structural and functional checks to allow full-chip verification of power-efficient designs
  • Tempus™ Timing Signoff Solution: Provides integrated, advanced process delay calculation and static timing analysis (STA) that achieves Samsung’s accuracy requirements, including those at low voltage operation
  • Voltus™ IC Power Integrity Solution: Cell-level power integrity tool that supports comprehensive electromigration and IR drop (EM/IR) design rules and requirements while providing full-chip system-on-chip (SoC) power signoff accuracy
  • Physical Verification System: Includes advanced technologies and rule decks to support design rule checking (DRC), layout versus schematic (LVS), smart metal fill, yield scoring, voltage-dependent checks, and in-design signoff
  • Litho Physical Analyzer: Enables designers to detect and automatically repair process hotspots to improve design manufacturability and yield of digital, custom and mixed-signal designs, libraries and IP. This is part of Samsung’s foundry DFM offering.
  • Cadence CMP Predictor: Predicts the 3D topology variation and hotspots caused by chemical mechanical polishing (CMP) to improve design manufacturability and reduce topology variation. This is part of Samsung’s foundry DFM offering.
  • LDE Electrical Analyzer: Allows layout-dependent effect- (LDE-) aware re-simulation, layout analysis, matching constraint checking, reporting on LDE contributions, and the generation of fixing guidelines from partial layout to accelerate analog design convergence
  • Modus™ Test Solution: Provides scan and logic/memory built-in self test (BIST) insertion, combined with a new physically aware 2D Elastic Compression architecture, enabling design engineers to achieve reductions in test time to minimize production test cost

For more information on Cadence digital and signoff solutions, please visit https://www.cadence.com/en_US/home/solutions/advanced-node-solutions.html.

“Samsung and Cadence collaborated closely on this new 10LPP process reference flow to provide our mutual customers with a fast path to design closure,” said Jaehong Park, senior vice president of the Design Service Team at Samsung Electronics. “Cadence’s digital and signoff tools have implemented methodology innovations that enable designers to access and reap the benefits of our 10LPP process.”

“Samsung’s certification of the Cadence digital tools enables customers to manage and overcome complexity and deliver advanced 10LPP designs faster,” said Dr. Anirudh Devgan, senior vice president and general manager of the Digital & Signoff Group and the System & Verification Group at Cadence. “Customers using the Cadence flow on Samsung’s latest 10LPP process can also achieve optimal power, performance and area (PPA) to meet their aggressive time-to-market requirements.”

About Cadence

Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry. More information about the company, its products and its services is available at www.cadence.com.

For more information, please contact:

Cadence Newsroom
408-944-7039
newsroom@cadence.com

© 2016 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.

Media Contacts

For more information, please contact:

Cadence Newsroom

408.944.7039

newsroom@cadence.com

A Great Place to Do Great Work!

Sixth year on the FORTUNE 100 list

Our Culture Join The Team
  • Products
  • Custom IC and RF
  • Digital Design and Signoff
  • IC Package
  • IP
  • PCB Design
  • System Analysis
  • Verification
  • All Products
  • Company
  • About Us
  • Leadership Team
  • Investor Relations
  • Alliances
  • Careers
  • Cadence Academic Network
  • Supplier
  • Media Center
  • Events
  • Newsroom
  • Designed with Cadence
  • Blogs
  • Forums
  • Contact Us
  • General Inquiry
  • Customer Support
  • Media Relations
  • Global Office Locator

Stay Connected

Please confirm to enroll for subscription!

Stay Connected

Thank you for subscribing. You will get an email to confirm your subscription.

© 2021 Cadence Design Systems, Inc. All Rights Reserved.

Terms of Use Privacy US Trademarks Do Not Sell My Personal Information
Connect with us