Cadence Announces General Availability of Tensilica Xtensa LX7 Processor Architecture, Increasing Floating-Point Scalability with 2 to 64 FLOPS/Cycle

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced general availability of the 12^th generation Tensilica^® Xtensa^® base processor architecture. The Xtensa LX7 architecture makes new technologies available for customization by Xtensa customers and increases floating-point choices from 2 to 64 FLOPS/cycle, meeting the growing need for precision and portability in today’s demanding DSP (digital signal processing) applications. The Xtensa LX7 architecture includes easy-to-use click-box options for the Tensilica Vision P6 DSP for image and convolutional neural network (CNN) processing, the Tensilica Fusion G3 DSP for multi-purpose fixed- and floating-point applications, and enhancements for the industry-leading ConnX BBE DSPs for baseband and radar applications with optional vector floating-point units.

The Xtensa LX7 release eases system-on-chip (SoC) design challenges with numerous architectural enhancements such as broader support for the AXI protocol and a new integrated DMA controller option, simplifying the integration of Xtensa DSP specialized offload engines with general-purpose application processors and GPUs and the associated complex interconnect fabrics. The new Xtensa LX7 processor is available now. For more information, visit www.cadence.com/go/lx7.

The Xtensa LX7 release also provides new tools, including a new hardware floating-point application binary interface (ABI) for increased floating-point C/C++ performance, as well as compiler and C library enhancements to add C99 complex float support.

Additional memory protection choices include:

• Support for ACE-Lite to facilitate  I/O coherence in heterogeneous mulit-processor designs
• Error-correcting code (ECC) on AXI interface to detect and correct bit errors in system memory
• Security to indicate the privilege and security level of the bus transaction
• Exclusive access for data integrity, preventing shared memory overwrite issues
• New automatically generated integrated DMA (iDMA) controller internal to the Xtensa processor to offload memory-to-memory data transfer operations from the processor and hide system bus latency. Includes a software library for ease-of-programming
• New fine-grained memory protection unit (MPU) with programmable region sizes and access protections

“The Tensilica Xtensa LX7 architecture has made significant improvements to its floating point scalability to address evolving challenges with various applications, truly making it one of the most configurable processors in the market,” said Steve Roddy, senior group director of Tensilica IP at Cadence. "Cadence continues its history of innovation by providing one of the most popular licensable processor architectures, which our customers use to create world-class products spanning from sensors to LTE modems to augmented reality devices. ”

“Many customers are looking for high-performance, power-efficient DSPs or deeply embedded controllers with accompanying tools and ecosystem support,” said Linley Gwennap, principal analyst of The Linley Group. “Cadence’s new Xtensa LX7 architecture meets these needs and is well-suited for emerging applications that demand more floating-point performance.”

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