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  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Integrity 3D-IC Platform
          • Cadence Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Voltus IC Power Integrity Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
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          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • 112G/56G SerDes
          • Chiplet and D2D
          • Denali Memory Interface and Storage IP
          • Interface IP
          • PCIe and CXL
          • Tensilica Processor IP
        • RESOURCES
          • Discover PCIe
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • Multiphysics System Analysis
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
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          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Fidelity CFD
          • Sigrity Advanced SI
          • Celsius Advanced PTI
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          • System Analysis Resources Hub
          • AWR Free Trial
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      • PCB Design and Analysis
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          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
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          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • Allegro X Design Platform
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  • 14 Mar 2016

Cadence Announces Availability of Complete IC Packaging Design and Analysis Solutions for Advanced Fan-Out Wafer-Level Chip Scale Packaging

Cross-fabric optimization accelerates multi-chip integration for smaller, lighter, power-optimized wireless mobile devices

SAN JOSE, Calif., 13 Mar 2016

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced the availability of the industry's only foundry-proven IC packaging design and analysis solutions for advanced Fan-Out Wafer-Level Chip Scale Packaging (WLCSP) and 2.5D interposer-based designs. The new capabilities enable the faster multi-chip integration that is ideal for smaller, lighter and power-optimized wireless mobile devices.

This complete IC packaging design and analysis solution includes the Cadence® OrbitIOTM Interconnect Designer, Cadence System-in-Package (SiP) Layout and Cadence Physical Verification System (PVS). This set of offerings enables multi-substrate interconnect pathway design, refinement, implementation and manufacturing verification and signoff spanning die I/O pad rings through IC package to system PCB.

The new Cadence SiP Layout WLCSP option integrated with PVS provides generic silicon wafer-based packaging methodologies previously validated by TSMC for their Integrated Fan-Out (InFO) process. Enhancements to OrbitIO Interconnect Designer strengthen 2.5D interposer package design support, providing optimal multi-die, single package interconnect integration. This enables higher performance for multi-substrate integrated devices with minimal size optimized for signal performance. For more information on the Cadence IC packaging design and analysis solution, visit www.cadence.com/news/ICpackaging172.

"Wireless mobility and wireless-enabled is the trend at all levels of electronic-centric products, from smartphones to cars to home appliances and beyond. They all need thin, lightweight, low-power yet high-performance devices at their core. This is the sweet spot for WLCSP, fueling its predicted explosion in adoption," said Steve Durrill, senior product engineering group director for the PCB Group at Cadence. "Our latest release enables broad WLCSP-enabled design and foundry and OSAT manufacturing signoff, which in turn helps fabless semiconductor and systems companies deliver ultra-thin mobile-focused devices using the latest foundry and OSAT IC package manufacturing approaches."

About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

For more information, please contact:
Cadence Newsroom
408-944-7039
newsroom@cadence.com


© 2016 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and the Cadence logo are registered trademarks and OrbitIO is a trademark of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.

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For more information, please contact:

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newsroom@cadence.com

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