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  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Genus Synthesis Solution
          • Conformal Smart LEC
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
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          • Circuit Simulation
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          • Spectre X Simulator
          • Virtuoso RF Solution
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus IC Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Emulation and Prototyping
          • Formal and Static Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • JasperGold Formal Verification Platform
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
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          • Flows
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          • Interface IP
          • Denali Memory IP
          • Tensilica Processor IP
          • Analog IP
          • System / Peripherals IP
          • Verification IP
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        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
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          • SI/PI Analysis
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          • Flows
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          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Omnis
          • Sigrity Advanced SI
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          • System Analysis Resources Hub
          • AWR Free Trial
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  • 07 Oct 2015

Imec and Cadence Complete Tapeout of First 5nm Test Chip

Cadence Innovus Implementation System Enables Optimal PPA for Advanced Designs

LEUVEN, Belgium and SAN JOSE, Calif., 06 Oct 2015

Nano-electronics research center imec and Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that the companies completed the first tapeout of a 5nm test chip using extreme ultraviolet (EUV) as well as 193 immersion (193i) lithography. To produce this test chip, imec and Cadence optimized design rules, libraries and place-and-route technology to obtain optimal power, performance and area (PPA) scaling via Cadence® Innovus™ Implementation System. Using a processor design, imec and Cadence successfully taped out a set of designs using EUV lithography as well as Self-Aligned Quadruple Patterning (SAQP) for 193i lithography, where metal pitches were scaled from the nominal 32nm pitch down to 24nm to push the limit of patterning.

The Innovus Implementation System is a next-generation physical implementation solution that enables system-on-chip (SoC) developers to deliver designs with best-in-class PPA while accelerating time to market. Driven by a massively parallel architecture with breakthrough optimization technologies, the Innovus Implementation System provides typically 10 to 20 percent better PPA and up to 10X full-flow speedup and capacity gain. For more information on the Innovus Implementation System, please visit www.cadence.com/news/innovus.

"Our collaboration with Cadence plays an important part in the development of the world's most advanced geometries including 5nm and below," said An Steegen, senior vice president of Process Technology at imec. "Together, we developed the necessary technology to enable tapeouts for advanced technology nodes such as this test chip. The Cadence next-generation platform is easy to use, which helps our engineering team stay productive in developing the rule set for advanced nodes."

"By achieving this milestone, Cadence and imec continue to demonstrate our dedication toward pushing patterning technologies to increasingly smaller nodes," said Dr. Anirudh Devgan, senior vice president and general manager of the Digital and Signoff Group at Cadence. "With imec technology and the Cadence Innovus Implementation System, we've created a working flow that can pave the way for developing innovative next-generation mobile and computer advanced-node designs."


About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry. More information about the company, its products and its services is available at www.cadence.com.

About imec
Imec performs world-leading research in nanoelectronics. Imec leverages its scientific knowledge with the innovative power of its global partnerships in ICT, healthcare and energy. Imec delivers industry-relevant technology solutions. In a unique high-tech environment, its international top talent is committed to providing the building blocks for a better life in a sustainable society. Imec is headquartered in Leuven, Belgium, and has offices in Belgium, the Netherlands, Taiwan, USA, China, India and Japan. Its staff of about 2,200 people includes almost 700 industrial residents and guest researchers. In 2014, imec's revenue (P&L) totaled 363 million euro. Further information on imec can be found at www.imec.be. Stay up to date about what's happening at imec with the monthly imec magazine, available for tablets and smartphones (as an app for iOS and Android), or via the website www.imec-int.com/en/imec-magazine.

For more information, please contact:
Cadence Newsroom
408-944-7039
newsroom@cadence.com

imec:
Hanne Degans, press officer and communications specialist
T: +32 16 28 17 69
Mobile: +32 486 06 51 75
Hanne.Degans@imec.be


© 2015 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and the Cadence logo are registered trademarks and Innovus is a trademark of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.

Imec is a registered trademark for the activities of IMEC International (a legal entity set up under Belgian law as a "stichting van openbaar nut"), imec Belgium (IMEC vzw supported by the Flemish Government), imec the Netherlands (Stichting IMEC Nederland, part of Holst Centre which is supported by the Dutch Government), imec Taiwan (IMEC Taiwan Co.)and imec China (IMEC Microelectronics (Shanghai) Co. Ltd.) and imec India (Imec India Private Limited).

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newsroom@cadence.com

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