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  • China - 简体中文
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  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Integrity 3D-IC Platform
          • Cadence Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Voltus IC Power Integrity Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • 112G/56G SerDes
          • Chiplet and D2D
          • Denali Memory Interface and Storage IP
          • Interface IP
          • PCIe and CXL
          • Tensilica Processor IP
        • RESOURCES
          • Discover PCIe
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • Multiphysics System Analysis
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Fidelity CFD
          • Sigrity Advanced SI
          • Celsius Advanced PTI
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          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
      • Embedded Software
      • PCB Design and Analysis
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          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
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          • Allegro Package Designer Plus
          • Allegro PCB Designer
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  • 05 Mar 2014

Cadence Announces New Allegro TimingVision Environment to Speed Timing Closure of High-Speed PCB Interfaces by up to 67%

SAN JOSE, Calif., 04 Mar 2014

Highlights:
  • TimingVision environment provides an innovative and unique environment for accelerating timing closure within the Allegro PCB Designer solution
  • Auto-interactive routing capabilities working with TimingVision environment accelerates timing closure on complex high-speed interfaces, such as DDR3 memory, by up to 67%
  • Allegro Sigrity users can combine TimingVision with Sigrity power-aware signal integrity (SI) analysis to rapidly implement and accurately assure compliance with memory interface specifications
  • Cadence enables product creation from IP to SoC to package to PCB to system, predictably and cost effectively
Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced new Allegro® TimingVision™ environment, which speeds up timing closure by up to 67%. Available within Cadence® Allegro PCB Designer, TimingVision environment makes it possible for PCB designers to save significant time in ensuring that signals in an interface meet timing requirements. This is an increasingly important capability as data rates increase and supply voltages decrease in today's advanced protocols, including DDR3/DDR4, PCI Express, and SATA.

TimingVision environment uses an embedded timing engine to analyze the entire interface structure and develop timing goals to help designers visualize real-time delay and phase information directly on a canvas. This greatly reduces manual editing, overall implementation time and designer effort. When combined with the Cadence Sigrity™ power-aware SI analysis tool, TimingVision environment enables rapid implementation and tuning in compliance with standard interfaces, diminishing trials and errors in fixing timing issues.

TimingVision environment is ideal for any PCBs that include advanced high-speed interfaces and is especially suited to PC, tablet, smartphone and cloud data center infrastructure applications. Key features include:
  • TimingVision environment, which provides dynamic feedback on the active and related signals during edits on the design canvas
  • Auto-interactive Phase Tuning (AiPT), to compensate both static and dynamic phase constraints on a selected set of differential pairs
  • Auto-interactive Delay Tuning (AiDT), to compensate for propagation delay, relative propagation delay and total etch length constraints specified in the physical design on a selected set of signals such as a byte lane.
"Using this new Allegro technology ended our frustrations over all of the time we were spending on routing and tuning. All of the hours we're saving as a team can be directed toward new project requests for the business," said Sky Huang, deputy director of computer-aided engineering at Pegatron.

"Cadence is in a unique position to address all high-speed IP implementation and verification needs, from chip to end product," said AJ Incorvaia, vice president, R&D, Cadence. "With the introduction of TimingVision environment, PCB designers now have a proven and highly efficient solution to meet increasingly complex timing closure challenges."

TimingVision environment, along with the auto-interactive routing environment, is available now as part of the Allegro PCB High-Speed Option.

To learn more about TimingVision environment, please click here.

About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available here.

For more information, please contact:
Cadence Newsroom
408-944-7039
newsroom@cadence.com


© 2014 Cadence Design Systems, Inc. All rights reserved worldwide. Allegro, Cadence, Sigrity, and the Cadence logo are registered trademarks and TimingVision is a trademark of Cadence Design Systems, Inc. in the United States and other countries.

Media Contacts

For more information, please contact:

Cadence Newsroom

408.944.7039

newsroom@cadence.com

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