Highlights: - TimingVision environment provides an innovative and unique environment for accelerating timing closure within the Allegro PCB Designer solution
- Auto-interactive routing capabilities working with TimingVision environment accelerates timing closure on complex high-speed interfaces, such as DDR3 memory, by up to 67%
- Allegro Sigrity users can combine TimingVision with Sigrity power-aware signal integrity (SI) analysis to rapidly implement and accurately assure compliance with memory interface specifications
- Cadence enables product creation from IP to SoC to package to PCB to system, predictably and cost effectively
Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced new Allegro® TimingVision™ environment, which speeds up timing closure by up to 67%. Available within Cadence® Allegro PCB Designer, TimingVision environment makes it possible for PCB designers to save significant time in ensuring that signals in an interface meet timing requirements. This is an increasingly important capability as data rates increase and supply voltages decrease in today's advanced protocols, including DDR3/DDR4, PCI Express, and SATA.
TimingVision environment uses an embedded timing engine to analyze the entire interface structure and develop timing goals to help designers visualize real-time delay and phase information directly on a canvas. This greatly reduces manual editing, overall implementation time and designer effort. When combined with the Cadence Sigrity™ power-aware SI analysis tool, TimingVision environment enables rapid implementation and tuning in compliance with standard interfaces, diminishing trials and errors in fixing timing issues.
TimingVision environment is ideal for any PCBs that include advanced high-speed interfaces and is especially suited to PC, tablet, smartphone and cloud data center infrastructure applications. Key features include:
- TimingVision environment, which provides dynamic feedback on the active and related signals during edits on the design canvas
- Auto-interactive Phase Tuning (AiPT), to compensate both static and dynamic phase constraints on a selected set of differential pairs
- Auto-interactive Delay Tuning (AiDT), to compensate for propagation delay, relative propagation delay and total etch length constraints specified in the physical design on a selected set of signals such as a byte lane.
"Using this new Allegro technology ended our frustrations over all of the time we were spending on routing and tuning. All of the hours we're saving as a team can be directed toward new project requests for the business," said Sky Huang, deputy director of computer-aided engineering at Pegatron.
"Cadence is in a unique position to address all high-speed IP implementation and verification needs, from chip to end product," said AJ Incorvaia, vice president, R&D, Cadence. "With the introduction of TimingVision environment, PCB designers now have a proven and highly efficient solution to meet increasingly complex timing closure challenges."
TimingVision environment, along with the auto-interactive routing environment, is available now as part of the Allegro PCB High-Speed Option.
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