Cadence® Conformal® Equivalence Checker (EC) is the industry’s most widely supported independent equivalence checking product. Conformal EC exhaustively verifies multi-million–gate ASICs and FPGAs several times faster than traditional gate-level simulation, enabling faster, more accurate bug detection and correction throughout the entire design flow.
With the industry’s only complete equivalence checking solution for verifying SoC designs—from RTL to final LVS netlist (SPICE) as well as FPGA designs—Conformal EC enables designers to verify the widest variety of circuits, including complex arithmetic logic, datapaths, memories, and custom logic, reducing your risk of missing critical bugs.
Join Cadence Education Services and Principal Education Application Engineer, Krishna Atreya for our free, one-hour live webinar “Getting the Bugs Out with Conformal EC.”
We’ll be exploring:
- Important features of the Conformal EC tool
- Key ways in which Conformal EC can speed up design verification
- Identify a few tips to speed up the equivalence checking task
To register for the “Getting the Bugs Out with Conformal EC” webinar, use the REGISTER button and sign in with your email and Cadence password, then select “Request” to register for the session. Once registered, you’ll receive a confirmation email containing all log-in details.
- Registration closes Tuesday, 29 October.
- Please ensure that you have received the log-in link / details by this date.
- Space is limited for this webinar—if you register, please plan on attending.
For questions and inquiries, or issues with registration, reach out to us:
- Europe, Middle East, and Africa: email@example.com
- India: Vishwanath K: firstname.lastname@example.org
- Asia Pacific: Cathy Li: email@example.com
To view our complete training offerings, visit the Education Services website.