Join Cadence® Training and Product Engineering Architect Joerg Mueller and Senior Application Engineer Tom Weiss for this free technical training webinar.
As a chip designer, you’re probably spending as much headspace on security threats as you are on traditional challenges like power, speed, and functionality. Recent microarchitectural vulnerabilities like “Meltdown” and “Row Hammer” that expose secure information like decryption keys were found only in post-silicon tapeout. This shows that conventional simulation-based verification is insufficient to address today’s security concerns.
Cadence’s JasperGold® Formal Verification Platform introduces formal verification to help address today’s growing security challenges by analyzing functional SVA properties as well as secure path propagation properties. In this webinar, we’ll focus on the JasperGold Security Path Verification (SPV) App that enables users to describe undesired leakage or corruption of secure data with dedicated SPV properties and prove the absence of such propagation paths using formal analysis. You’ll experience how security is confirmed—or its leakage paths are presented—using “taint” in the JasperGold Visualize™ waveform viewer.
- Background and Security Requirements
- JasperGold SPV App Overview
- Usage Examples
- Success Stories
Date and Time
Thursday, October 7
08:00 PDT / 16:00 BST / 17:00 CEST / 20:30 IST / 23:00 CST
To register for the “Addressing Security Verification Requirements with JasperGold SPV App” webinar, use the REGISTER button below and sign in with your Cadence Support account (email ID and password) to login to the Learning and Support System. Then select “Enroll” to register for the session. Once registered, you’ll receive a confirmation email containing all login details.
For questions and inquiries, or issues with registration, reach out to us:
- Europe, Middle East, and Africa: email@example.com
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- India: Preeti P Gowda
- China: Cathy Li
- Japan: Yuji Shimazaki
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07 Oct 2021