Past Events

ChipEx User Conference 2021

ChipEx is the largest annual event of the Israeli semiconductor industry, and Cadence will be attending as a major track sponsors in these two topics: Tensilica and Verification. Join us at this event and hear from our experts!

CadenceTECHTALK: JasperGold RTL Designer Apps (Superlint/CDC) を使って高品質RTLを前倒しでサインオフ！

JasperGold® RTL Designer Appsをご説明します。テストベンチが存在しない段階であっても、フォーマル検証についての詳細な知識のないエンジニアであっても、Superlint Appで「ポカ除け」を、CDC Appで非同期検証を行うことができます。

CadenceTECHTALK: Improving Debug Productivity

In this webinar, you will learn how the Indago Debug Analyzer is addressing debug performance and throughput concerns by introducing higher performance waveform dumping, better UVM debugging capabilities, faster startup times even with large SoCs, and responsive search and driver tracing capabilities.

CadenceTECHTALK:Fast, Accurate, and Integrated EM Analysis with EMX Planar 3D Solver V6​ (Taiwan) ​

Join Cadence experts for a free one-hour webinar to hear the newest features of EMX Planar 3D Solver Version 6 and how it is integrated into Cadence Virtuoso® environment. Electromagnetic (EM) simulation is a critical part of modern, analog chip design. Traditional RC extraction tools typically have limitations as frequencies of operation and performance specifications are increased. Learn why Cadence EMX Planar 3D Solver is a best-in-class EM simulator for silicon chip devices.

Training Webinar: Using Specman e Reflection!

Join Cadence Training and Software Architect Efrat Shneydor for this free technical Training Webinar. Reflection is a unique capability in the e language, providing a deep inspection of the program, going into the verification environment code and structure, and letting you examine defined types, query current values of instances, and more. This introductory webinar will explain e reflection syntax—along with many code examples and explore how to write queries of the type system.

CadenceTECHTALK: Maximizing Custom Layout Productivity Even as the Circuit Changes

Through implementing the layout of a carefully matched current mirror block in this CadenceTECHTALK, we will show how this improved standard functionality can give you significant speedups during the P&R phases, as it applies both to the initial implementation as well as to handling ECOs.

CadenceTECHTALK: Faster Design Closure with Integrated Full-Flow Physical Signoff Solution

In this CadenceTECHTALK, we will cover how the Pegasus Verification System capabilities are leveraged for in-design signoff DRC, LVS, and metal, and PG fills within the Innovus Implementation System. We will also show how the Innovus and Pegasus systems work together as an integrated signoff fill flow. The hierarchical metal fill flow is an automated timing-aware flow to add signoff metal fill in the Innovus system, while in-design PG fill maximizes effective PG stripes to reduce IR drop hotspots. This in-design physical signoff closure flow with Cadence tools delivers fastest signoff convergence with best available PPA.

CadenceTECHTALK：业界领先的Tensilica ConnX B20 DSP – 专为雷达、激光雷达和通信处理设计

This webinar will introduce the Tensilica ConnX B20 DSP. We are looking forwarding to your participation.

CadenceTECHTALK: Boost Verification Productivity with PSS 2.0 and Perspec

In this webinar, we will review the main principles of PSS 2.0 and demonstrate how Cadence® Perspec™ System Verifier helps to boost productivity of creating SoC level tests by IP level content re-use, automatic use-case amplification and correct-by-construction generation of complex concurrent multi-core/multi-threaded tests.

On-demand CadenceTECHTALK: SoCの性能テストを shift left! "System VIP"のご紹介

SoC検証における課題を確認しながら、ケイデンスのSystem VIPを利用することで、それらの課題を如何に軽減できるかを、プロセッサベースデザインにおける性能検証をケーススタディとしてご紹介します。