DesignCon 2019

29 Jan 2019 - 31 Jan 2019

Santa Clara, CA, USA

Visit us at DesignCon in booth 711 to see how you can address your design challenges with Cadence^® Sigrity^™ signal integrity and power integrity (SI/PI) tools, multi-gigabit SerDes analysis, advanced DDR IP and design/analysis tools, automated IBIS-AMI model creation, integrated electronics/photonic design automation, and advanced IC packaging and cross-platform solutions. Selected proceedings are available below.

See Cadence booth demos highlighting:

Thermal-aware PI design and analysis including multi-level tree-topology set-up from PCB schematics
Power-aware SI analysis of next-generation GDDR and LPDDR interfaces using IBIS-AMI models
Streamlining multi-gigabit SI and 3D interconnect extraction across PCB-connector interfaces for TX-to-RX interface compliance
Advanced packaging and cross-platform solutions for next-generation 2.5D and 3D-IC design
112G long-reach SerDes for next-generation datacenter applications

Attend Cadence conference presentations on:

Panels and sponsored sessions available to all attendees.

Date and Time	Topic	Speaker
Tuesday, January 29 4:45pm – 6:00pm Ballroom D	Panel – Photonics Coming of Age: The Emergence of PDKs	James Pond, CTO, Lumerical Gilles Lamant, Distinguished Engineer, Cadence Mohamed Youssef, Foundry Enablement Manager, Mentor Samir Chaudhry, Director, Design Enablement, TowerJazz Ashkan Sevedi, Photonics Research Scientist, Hewlett Packard Enterprise Rui Santos, Principal Scientist, SMART Photonics
Wednesday, January 30 3:45pm – 5:00pm Ballroom D	Panel – Real World Cloud and Machine Learning/AI Deployment for Hardware Design	Christopher Cheng, Distinguished Technologist, Hewlett Packard Enterprise Norman Chang, CTO, Ansys Wendem Beyene, Principal Engineer, Intel Chekib Akrout, Corporate VP, Strategic Programs, Synopsys David White, Senior Group Director R&D, Cadence
Thursday, January 31 8:05am – 8:45am Great America 3	Modeling and Simulation Challenges for 16Gbps GDDR6 Interfaces View Presentation	Chung Huang and Kancy Robison, Cadence
Thursday, January 31 9:05am – 9:45am Great America 3	Analyzing LPDDR4X Interfaces Using Circuit and Channel Simulation: A Case Study View Presentation	Snehamay Sinha, Texas Instruments
Thursday, January 31 10:05am – 10:45am Great America 3	Exposing Adaptive Equalization Functionality in 32 Gbps Receivers View Presentation	Greg Edlund, IBM
Thursday, January 31 11:05am – 11:45am Great America 3	DC Analysis Automation for Multi-level Tree Topology View Presentation	Songping Wu, Google
Thursday, January 31 2:00pm – 2:40pm Great America 3	Modeling and Simulating 112Gbps SerDes View Presentation	Manuel Luschas, Ken Willis, and Margaret Johnson, Cadence
Thursday, January 31 2:50pm – 3:30pm Great America 3	Advanced Package Design Sign-off Reference Flow View Presentation	Sungwook Moon Ph.D. and Max Min Ph.D., Samsung Foundry
Thursday, January 31 3:45pm – 4:25pm Great America 3	System Planning and Management for 3D Designs View Presentation	TV Narayanan, Cadence
Thursday, January 31 3:45pm – 5:00pm Ballroom D	Panel – Which Model When? Succeeding with IBIS-AMI	Donald Telian, Owner/SI Consultant, SIGuys Walter Katz, Chief Scientist, Signal Integrity Software Inc. Michael Mirmak, Technical Lead, Signal Integrity, Intel Corp. Ken Willis, Product Engineering Architect, Cadence

These sessions are available to 2-Day Pass (excluding Tutorials), All-Access Pass, and Alumni All-Access Pass holders.

Date and Time	Topic	Speaker
Tuesday, January 29 9:00am – 12:00pm Ballroom A	Tutorial – Advanced IBIS-AMI Techniques for 32 GT/s and; Beyond	Greg Edlund, Senior Engineer, IBM Kumar Keshavan, Software Architect, Cadence Mehdi Mechaik, Staff Application Engineer, Cadence Ambrish Varma, Senior Principal Software Engineer, Cadence Ken Willis, Product Engineering Architect, Cadence
Tuesday, January 29 9:00am – 12:00pm Ballroom B	Tutorial – Lowering the Barrier to Entry for Electronic/Photonic ICs	James Pond, CTO, Lumerical Gilles Lamant, Distinguished Engineer, Cadence Samir Chaudhry, Director, Design Enablement, TowerJazz Kerry Schutz, MathWorks
Wednesday, January 30 8:00am – 8:45am Ballroom C	Mode Conversion and Its Impact on 112-Gbps PAM4 Systems	Jason Chan, Senior Principal Engineer, Cadence Hong Anh, Signal Integrity Engineer, Xilinx Geoff Zhang, Distinguished Engineer and Supervisor, Xilinx Min Huang, Design Engineer, Xilinx
Wednesday, January 30 9:00am – 9:45am Ballroom B	Design Space Exploration with Polynomial Chaos Surrogate Models for Analyzing Large System Designs	Majid Ahadi Dolatsara, Student, Georgia Institute of Technology Ambrish Varma, Senior Principal Software Engineer, Cadence Kumar Keshavan, Senior Software Architect, Cadence Madhavan Swaminathan, Professor, Georgia Institute of Technology
Wednesday, January 30 9:00am – 9:45am Ballroom E	Effect of Power Plane Inductance on Power Delivery Networks View Presentation	Shirin Farrahi, Principal Software Engineer, Cadence Mehdi Mechaik, Staff Application Engineer, Cadence Ethan Koether, Hardware Engineer, Oracle Istvan Novak, Principle Signal and Power Integrity Engineer, Samtec

Questions About this Event?

Send email to events@cadence.com

Event Details

29 Jan 2019 - 31 Jan 2019

DesignCon 2019

Santa Clara Convention Center
Santa Clara, CA, USA

For more details view the
DesignCon 2019 website

DesignCon and the Future of Sigrity Tools

Brad Brim, Cadence product engineering architect, talks about DesignCon highlights, changes in signal integrity (SI) over the years, SI’s growing importance in system design, and the future direction of Sigrity technology.

Questions about this event?

Send email to: events@cadence.com