Visit us at DesignCon in booth 711 to see how you can address your design challenges with Cadence® Sigrity™ signal integrity and power integrity (SI/PI) tools, multi-gigabit SerDes analysis, advanced DDR IP and design/analysis tools, automated IBIS-AMI model creation, integrated electronics/photonic design automation, and advanced IC packaging and cross-platform solutions. Selected proceedings are available below.
See Cadence booth demos highlighting:
- Thermal-aware PI design and analysis including multi-level tree-topology set-up from PCB schematics
- Power-aware SI analysis of next-generation GDDR and LPDDR interfaces using IBIS-AMI models
- Streamlining multi-gigabit SI and 3D interconnect extraction across PCB-connector interfaces for TX-to-RX interface compliance
- Advanced packaging and cross-platform solutions for next-generation 2.5D and 3D-IC design
- 112G long-reach SerDes for next-generation datacenter applications
Attend Cadence conference presentations on:
Panels and sponsored sessions available to all attendees.
Date and Time |
Topic |
Speaker
|
---|---|---|
Tuesday, January 29 |
James Pond, CTO, Lumerical |
|
Wednesday, January 30 |
Panel – Real World Cloud and Machine Learning/AI Deployment for Hardware Design |
Christopher Cheng, Distinguished Technologist, Hewlett Packard Enterprise |
Thursday, January 31 |
Modeling and Simulation Challenges for 16Gbps GDDR6 Interfaces |
Chung Huang and Kancy Robison, Cadence |
Thursday, January 31 |
Analyzing LPDDR4X Interfaces Using Circuit and Channel Simulation: A Case Study |
Snehamay Sinha, Texas Instruments |
Thursday, January 31 |
Exposing Adaptive Equalization Functionality in 32 Gbps Receivers |
Greg Edlund, IBM |
Thursday, January 31 |
DC Analysis Automation for Multi-level Tree Topology |
Songping Wu, Google |
Thursday, January 31 |
Modeling and Simulating 112Gbps SerDes |
Manuel Luschas, Ken Willis, and Margaret Johnson, Cadence |
Thursday, January 31 |
Advanced Package Design Sign-off Reference Flow |
Sungwook Moon Ph.D. and Max Min Ph.D., Samsung Foundry |
Thursday, January 31 |
System Planning and Management for 3D Designs |
TV Narayanan, Cadence |
Thursday, January 31 |
Donald Telian, Owner/SI Consultant, SIGuys |
These sessions are available to 2-Day Pass (excluding Tutorials), All-Access Pass, and Alumni All-Access Pass holders.
Date and Time |
Topic |
Speaker |
---|---|---|
Tuesday, January 29 |
Tutorial – Advanced IBIS-AMI Techniques for 32 GT/s and; Beyond |
Greg Edlund, Senior Engineer, IBM |
Tuesday, January 29 |
Tutorial – Lowering the Barrier to Entry for Electronic/Photonic ICs |
James Pond, CTO, Lumerical
|
Wednesday, January 30 |
Jason Chan, Senior Principal Engineer, Cadence |
|
Wednesday, January 30 |
Design Space Exploration with Polynomial Chaos Surrogate Models for Analyzing Large System Designs |
Majid Ahadi Dolatsara, Student, Georgia Institute of Technology |
Wednesday, January 30 |
Effect of Power Plane Inductance on Power Delivery Networks |
Shirin Farrahi, Principal Software Engineer, Cadence |
Questions About this Event?
Send email to events@cadence.com
Event Details
29 Jan 2019 - 31 Jan 2019
DesignCon 2019
Santa Clara Convention Center
Santa Clara, CA, USA
For more details view the
DesignCon 2019 website
DesignCon and the Future of Sigrity Tools
Questions about this event?
Send email to: events@cadence.com