CadenceTECHTALK: Xcelium ML for 5X Faster Regression Throughput

Join this webinar to learn how Xcelium ML can be a game changer for your verification flow, providing up to 5X regression throughput saving significant time and compute resources.

DVCon Europe 2021

Join Cadence at DVCon Europe, where Matt Graham will be discussing "Smarter Verification Management" on a 1-hour workshop and Kanwarpal Singh and Bijiendra Mittra, as they discuss "Accelerated Signoff with JasperGold RTL Designer Apps". The two-day virtual conference offers keynotes, panel sessions, insightful presentations and tutorials.

CadenceCONNECT Jasper User Group 2021

Ready to share and discuss the latest design and verification best practices with your peers from around the world? It’s time for our annual formal verification event CadenceCONNECT Jasper User Group.

CadenceTECHTALK: テンシリカ DSP IPウェビナーシリーズ

Vision・AI 処理向け Vision DSP、浮動小数点処理向けFloatingPoint DSP、オーディオ・ボイス・AI 処理向け HiFi DSP、そしてディープラーニング・AI 処理 向けの新しいDNA プロセッサについて、最近のアプリケーションのトレンドと要求性能なども交えながらテンシリカ IP の最新状況をご紹介します。

Linley Fall Processor Conference 2021

The Linley Conferences have been called the highest quality of their kind by previous attendees because they provide a unique opportunity to hear, question, and network with key providers of advanced technology products. Join Cadence this year and learn about our Tensilica offerings at our presentation and breakout session!

NAFEMS World Congress 2021

Join Cadence at NAFEMS World Congress. The conference will provide a forum for presenting a unique combination in innovative techniques and best practice methods that cover every aspect of engineering modelling, analysis and simulation. Check Cadence presentations in the conference as well as visit our virtual booth.

CadenceTECHTALK: Intelligent Cross-Platform Workflows for RF PCB Integration

This webinar will demonstrate the ways in which the AWR Design Environment V16 platform supports an RF-to-PCB workflow using a new unified library import wizard to convert Allegro PCB Editor symbols, footprints, and PCB technology file into an AWR process design kit (PDK) that can be used to create an Allegro technology-compatible RF design using standard design entry and simulation methods. Upon completion of the design, the RF engineer can export the schematic and layout of the sub-circuit with all the underlying hierarchy into a design library for direct integration into Allegro schematic capture and layout tools.

CadenceTECHTALK: Using Protium Black-Box Flow to Implement Native Interfaces

Join this webinar to learn how to get the highest possible prototype performance, the pros and cons of black-boxing, realization of full-speed interfaces on Protium.

CadenceTECHTALK: Power and Energy Optimization Using Tensilica IP

In this webinar, we will describe common challenges and solution in creating an efficient and accelerated flow that will meet technical requirements for accurately measure the power, the energy and system performance while making essential design trade-offs to meet aggressive time-to-market schedule.

CadenceTECHTALK: Joulesによる早期電力解析および自動電力削減

低消費電力化を実現するJoulesを用いたソリューションと最新機能をご紹介します。