Training Webinar: Solve Tricky SVA Problems with Jasper Visualize and WaveEdit

Join Cadence Training and Sr. Principal Education Application Engineer Mike Avery for this free technical Training Webinar. We’ll demonstrate how Jasper Visualize and WaveEdit provide an easy-to-use vehicle, so you can get the answers to your own questions—quickly and easily

SEMICON Japan 2022 - APCS 2022

ケイデンスのAdvanced Package向けの統合ソリューション（UCIe die-to-die (D2D) コネクティビティソリューション、Cadence 3D-IC設計ソリューション）をご覧ください。

HiFiLeD Symposium 2022

Join us at HiFiLeD Symposium in December 2022. The topics will be range from issues concerning the complexity, reliability, accuracy and uncertainties in generating the High-Fidelity LES/DNS data, to their application towards turbulence and transition modeling. It will include progress on the underlying high-order numerical methods (HOMs), innovative approaches for CPU acceleration for LES and DNS, exploitation of massive parallel architectures, efficient post-processing on massive parallel hardware, innovative machine learning methods, as well as experimental data. Moreover, the Symposium offers the opportunity to communicate and exchange knowledge for academic researchers, graduate students, industrial engineers, as well as industrial R&D managers and consultants working in the fields of turbulent flow modeling, simulations, measurements, and multidisciplinary CFD applications.

EDAPS 2022

Cadence is a Silver Sponsor at the IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) 2022 Virtual Conference. Designers and researchers share and discuss their work on all aspects of electrical packaging, including modeling, design and simulation, fabrication, and characterization.

DesignCon 2023

Cadence is a Platinum sponsor of DesignCon—the premier high-speed communications and system design conference. Visit us in Booth 733 to see how you can improve your electromagnetic, electronic, and thermal designs with system analysis, tackle advanced IC packaging and cross-platform challenges, accelerate RF to mmWave designs, and successfully incorporate photonic ICs and designs with 112G SerDes and DDR IP.

DVCon Europe 2022

Join Matt Graham, Product Engineering Group Director, on December 6 at 4pm for his presentation on Verification 2.0 – Multi-Engine, Multi-Run – AI-Driven Verification. This talk covers some of the near-term opportunities for applying AI and ML pragmatically to verification problems and presents potential future directions for AI and ML area. Be sure to visit booth #601 to learn how Cadence is leveraging big data and AI to optimize verification productivity and efficiency with the Verisium™ platform.

DATE 2023

The Design, Automation and Test in Europe (DATE) conference is the main European event bringing together designers and design automation users, researchers, and vendors, as well as specialists in the hardware and software design, test, and manufacturing of electronic circuits and systems. DATE puts a strong emphasis on both technology and systems, covering ICs/SoCs, reconfigurable hardware and embedded systems as well as embedded software.

CadenceTECHTALK: テンシリカIPセミナー

サブシステムに要求されるプリプロセッシング、AI推論、ポストプロセッシング、Always-On(AON)、レーダーなど、それぞれの処理に最適なテンシリカIPとそれらにおいて包括的にサポートされている機能安全、セキュリティ機能について、具体的なパフォーマンスや採用事例なども交えながらテンシリカIPの最新状況をご紹介します。

CadenceTECHTALK: チップ全体の最適化およびサインオフを10倍高速化するCertus Closure Solutionのご紹介

今年10月11日に発表した新製品Certus Closure Solutionを紹介いたします。並列分散同時処理によって、デザインの大きさに制限なく、タイミングおよびパワーの最適化を一晩で完了可能なソリューションの概要をユーザ事例と併せて説明いたします。

CadenceTECHTALK: Generate the Best Mesh Every Time – Automatically

Unstructured meshing can automate much of the mesh generation process, saving significant engineering time and cost. However, controlling numerical errors resulting from the discrete mesh requires adaptation to the developing solution. Join this webinar to learn how Cadence CFD mesh adaptation methods use a continuous-size field that gets updated as the solution progresses. As a result, adherence to the underlying CAD geometry is maintained, and mesh quality is ensured.