Date EVENT NAME TECHNOLOGY Location Event Type
24 Jun 2020

Webinar: Using Row-Based Methodology to Improve Advanced-Node Custom Layout

Join us for this webinar to learn about assisted place-and-route utilities for improving layout designer efficiency, automatic device-layer fill to meet complex layer density requirements, and how to route designs using width-based spacing track patterns to minimize DRC errors, coloring conflicts, and EM errors.

Advanced Node Design Online Cadence Event
05 Jun 2020 - 03 Jul 2020

Webinar: Tips and Tricks for Allegro PCB Designer

Join this webinar on Cadence Allegro PCB Designer technologies to learn the latest developments.

Allegro Online Cadence Event
03 Jun 2020

Webinar: Minimize Layout Iterations and EM Errors with Simulation-Driven Routing

Electromigration (EM) has a major impact on IC reliability and lifespan, and it poses additional challenges as we move to lower process nodes. In this webinar and demonstration, learn how to address EM concerns with simulation-driven routing (SDR). Built upon the Cadence® electrically aware design (EAD) technology, SDR provides immediate EM and parasitic feedback for developing layout geometries to connect components.

Virtuoso Online Cadence Event
17 Jun 2020

Webinar: Innovus Hierarchical Flow Overview and New 20.1 Features

In this webinar, the latest Innovus 20.1 features and improvements will be highlighted, including early hierarchical floorplan synthesis and hierarchical database innovations.This webinar is intended for Cadence customers who have access to the Digital Implementation flow.

Innovus, Digital Implementation Online Cadence Event
10 Jun 2020

Webinar: Getting the Most Out of Your Custom Waveforms

Want to get more out of your current tools? Join us for this webinar and discover how to get the most out of visualizing your waveforms in the Cadence Virtuoso ADE Product Suite.

Virtuoso Online Cadence Event
24 Jun 2020

Webinar: Extending PPA Using Machine Learning

During this webinar, we will explain how machine learning is being used as part of Innovus Implementation and for automated digital flow optimization. Join this session to learn more about machine learning technology and how to leverage these innovations to improve your digital design. This webinar is intended for Cadence customers who have access to the Digital Implementation flow.

Innovus, Digital Implementation Online Cadence Event
07 Jun 2020

Webinar: Extending Innovation with Innovus 20.1 Release (Hebrew)

The Cadence® Innovus™ Implementation System continues to extend technology innovation to ensure designers can complete ever larger and more complex designs. During this webinar, Cadence will share the latest Innovus Implementation 20.1 release technology highlights. Limited to Cadence customers with access to the digital implementation flow.

Innovus Online Cadence Event
10 Jun 2020

Webinar: Digital Implementation Flow Automation and Vivid Design Metrics Visualization

Attend this webinar to learn how to use Cadence flow kit and vivid metrics to improve productivity. This webinar is intended for Cadence customers who have access to the Digital Implementation flow.

Digital Implementation Online Cadence Event
11 Jun 2020

Webinar: Developing PCBs for Wireless Applications Leveraging EM Verification and an RF Design Flow

This webinar will showcase the use of the Cadence AWR Design Environment, specifically AWR AXIEM and AWR Microwave Office software, to enhance the design of PCB-based wireless functionality vis-à-vis interoperability with the Cadence Allegro platform.

RF Microwave Design Online Cadence Event
17 Jun 2020

Webinar: Creating Assertions for SV Real-Number Modeling

Join Cadence Training and Solutions Director Tim Pylant, for our free, one-hour live webinar “Creating Assertions for SV Real-Number Modeling”. In this webinar, we’ll outline the use of SVA to create MS assertions and show how they can be re-used from behavioral to circuit-level verification. We’ll also include an intro to the SVA language and show numerous examples of how to create assertions for common analog blocks.

Xcelium Online Cadence Event