VLSI Fundamentals: A Practical Approach Education Kit

• Summary: A full set of 20 modules with lecture slides and lab exercises (in selected modules) ready for use in a typical 10-12-week undergraduate course (full syllabus below).
• Modular and Flexible Use: Teaching staff have the freedom to choose which modules to teach – use all the modules in the Education Kit or only those that are most appropriate to your teaching outcomes.
• Level: Advanced. Students are required to have an understanding of digital electronics and the basics of hardware description language (Verilog).

This education kit has been created in collaboration with Arm. All software tools required for the practical part are available through the Cadence^® University Program.

Learning outcomes

Knowledge and understanding of

• The characteristics of the nonideal transistor due to high field effects, channel length modulation, threshold voltage effects, and leakage
• How to estimate the characteristics of CMOS circuits including noise margins, DC response, and RC delay models
• How to estimate the resistance and capacitance of on-chip wires and describe methods to optimize wire delay, power consumption, and crosstalk in on-chip wires
• The operation of CMOS latches and flip-flops and plan cell layouts using stick diagrams
• The limits imposed by timing constraints such as setup and hold time, propagation, and contamination delays in sequential circuits
• The importance of testing in chip design and the concepts of stuck-at fault, automatic test pattern generation (ATPG), and built-in self test (BIST)
• The different SRAM architecture
• The sources of power dissipation in a circuit and methods to control power losses
• The implications of clock distribution networks on skew and clock power consumption
• The sources and effects of on-chip variation
• How to simulate a circuit using SPICE to determine its DC transfer characteristics, Transient response and Power consumption

Intellectual

• Outline the key characteristics/features of nMOS and pMOS transistors and draw the cross-section of a CMOS inverter
• Use plots and cross-section diagrams to describe the current and voltage (I-V) characteristics of the MOS device when operating in cut off, linear, and saturation regions
• Describe the effects of technology scaling on the number and cost of transistor power dissipation in devices
• Explain logical effort and show how it can be applied in minimizing the delay of a combinational circuit path
• Explain and demonstrate techniques used to optimize combinational logic circuits for best critical paths and best delay/power tradeoffs for logic gates
• Describe and explain the features of different adder architectures, including carry-ripple adder, carry-skip adder, carry-lookahead adder, carry-select adder, carry-increment adder, and tree adder
• Design and describe the operation of data path circuits, such as comparators, shifters, and multi-input adders and multipliers
• Describe the operation of electrostatic discharge (ESD) protection circuits using their circuit diagram
• Describe the implementation of a simplified processor at abstraction levels, including architecture, microarchitecture, logic design, circuit design, physical design, verification, and test

Practical

• Design, implement, simulate, and verify simple logic gates from transistor-level schematic to layout
• Use NC-Verilog to simulate and verify the operation of logic blocks
• Use Cadence Genus™ Synthesis Solution to synthesize logic gates from hardware description language and use Cadence Innovus™ Implementation System to place and route logic design
• Assemble a chip from schematic, layout, add pad frame, and then tape out in GDSII format