CDNLive Silicon Valley 2018
April 10-11, 2018
Santa Clara Convention Center – Santa Clara, CA
CDNLive Silicon Valley brought together Cadence® technology users, developers, and industry experts for networking, sharing best practices on critical design and verification issues, and discovering new techniques for designing advanced silicon, SoCs, and systems.
Highlights of CDNLive Silicon Valley 2019:
Presentations
Choose from a wide variety of user-authored presentations addressing all aspects of design and IP creation, integration, and verification. Discover how others are using Cadence technologies and techniques to realize silicon, SoCs, and systems—efficiently and profitably.
Technology Overviews
Participate in a variety of interactive techtorials to get a more in-depth look at specific Cadence products, new solutions, and feature enhancements.
Keynote Speakers
Hear from industry leaders and visionaries who influence the global electronics marketplace. They will discuss trends in systems, silicon, and applications and share their thoughts on the challenges and opportunties that face us today.
Designer Expo
Learn more about the collaborative ecosystem available to support you. Cadence and our partners will showcase the latest results of our joint efforts. Explore new products and services from our many exhibitors.
Network Opportunites
Engage in stimulating technology discussions with your peers and stay connected after the conference.
Best Presentation Awards
Congratulations to our CDNLive Silicon Valley 2018 Best Presentation Award Winners!
Track: Front-End Design
FED102: Design Implementation of Technology IP Using High-Level Synthesis
Rajat Dhawan, Qualcomm
Track: Digital Implementation / Advanced Node
ADV201: Overcoming 7nm PG Challenges
Gaurav Ajwani, Barefoot Networks
Track: Signoff
SIG103: Pegasus Physical Verification Signoff at 16nm
Kyle Peavy, Texas Instruments
Track: Custom / Advanced Node
CUS207: 7nm Custom Design Reference Flow Based on Virtuoso WSP (Width Spacing Pattern)
Jignesh Patel, GLOBALFOUNDRIES
Sidd Devalapalli, GLOBALFOUNDRIES
Track: IP / Block Verification
IPB102: The Regression Watchdog: Great Collaboration Around vManager Deployment, Ends-Up with Real-Time Data Mining Tool
Alon Shtepel, Western Digital
Track: SoC / System Verification
VER102: Pre-Silicon SW/FW Testing with Protium S1 Platform: A Case Study
Horace Chan, Microsemi
Track: SI/PI and IC Packaging
PAC102: Simulate System (Chip-Package-PCB) Power Distribution Network (PDN) Using Sigrity OptimizePI Tool
Alex Tain, Seagate
Track: PCB Design and Simulation
PCB102: PSpice and MATLAB Co-Simulation Enables Maximizing DDR Power and Ground Impedance and Minimizing Power Supply Noise
Don Pakbaz, GLOBALFOUNDRIES
Track: PCB Design
DES203: Batch Checks Aren’t Early Enough: Real-Time DFM Checks to Get Done Faster, Sooner
Edgar Pambid, Arista Networks
Track: Mixed-Signal Design and Verification
MIX206: Mixed-Signal Verification Challenges and Solutions
Nilesh Sonara, Broadcom
Noorulla Mohammad, Broadcom
Track: Tensilica Processors and Design IP
DIP201: Architecting the Most Advanced Automotive SoCs: Maximizing Safety and Performance
John Bainbridge, NetSpeed Systems
Track: Academic
ACA201: Application of Machine Learning to EDA Problems
Madhavan Swaminathan, Georgia Institute of Technology
Contact Us
Questions?
Email cdnlive@cadence.com
