CDNLive Silicon Valley 2018
April 10-11, 2018
Santa Clara Convention Center – Santa Clara, CA
CDNLive Silicon Valley brought together Cadence® technology users, developers, and industry experts for networking, sharing best practices on critical design and verification issues, and discovering new techniques for designing advanced silicon, SoCs, and systems.
Highlights of CDNLive Silicon Valley 2018:
Technical Sessions
This year’s conference featured more than 100 presentations from 12 different technical tracks, including a wide variety of user-authored presentations addressing all aspects of design and IP creation, integration, and verification. Designers discovered how others are using Cadence technologies and techniques to design silicon, SoCs, and systems efficiently and profitably.
Keynote Speakers
Cadence CEO, Lip-Bu Tan, featured special guest speakers Rodrigo Liang, Co-Founder and CEO, SambaNova Systems and Dr. Gopal Raghavan, Co-Founder and CEO, Eta Compute. We closed out the keynote session with Tom Beckley, Senior Vice President and General Manager of the Custom IC & PCB Group at Cadence.
Designer Expo
More than 20 exhibitors participated in the Designer Expo, and highlighted the collaborative ecosystem available to support you. Cadence and our partners enjoyed 2 days mingling with customers and exploring joint solutions.
Best Presentation Awards
Congratulations to our CDNLive Silicon Valley 2018 Best Presentation Award Winners!
Track: Front-End Design
FED102: Design Implementation of Technology IP Using High-Level Synthesis
Rajat Dhawan, Qualcomm
Track: Digital Implementation / Advanced Node
ADV201: Overcoming 7nm PG Challenges
Gaurav Ajwani, Barefoot Networks
Track: Signoff
SIG103: Pegasus Physical Verification Signoff at 16nm
Kyle Peavy, Texas Instruments
Track: Custom / Advanced Node
CUS207: 7nm Custom Design Reference Flow Based on Virtuoso WSP (Width Spacing Pattern)
Jignesh Patel, GLOBALFOUNDRIES
Sidd Devalapalli, GLOBALFOUNDRIES
Track: IP / Block Verification
IPB102: The Regression Watchdog: Great Collaboration Around vManager Deployment, Ends-Up with Real-Time Data Mining Tool
Alon Shtepel, Western Digital
Track: SoC / System Verification
VER102: Pre-Silicon SW/FW Testing with Protium S1 Platform: A Case Study
Horace Chan, Microsemi
Track: SI/PI and IC Packaging
PAC102: Simulate System (Chip-Package-PCB) Power Distribution Network (PDN) Using Sigrity OptimizePI Tool
Alex Tain, Seagate
Track: PCB Design and Simulation
PCB102: PSpice and MATLAB Co-Simulation Enables Maximizing DDR Power and Ground Impedance and Minimizing Power Supply Noise
Don Pakbaz, GLOBALFOUNDRIES
Track: PCB Design
DES203: Batch Checks Aren’t Early Enough: Real-Time DFM Checks to Get Done Faster, Sooner
Edgar Pambid, Arista Networks
Track: Mixed-Signal Design and Verification
MIX206: Mixed-Signal Verification Challenges and Solutions
Nilesh Sonara, Broadcom
Noorulla Mohammad, Broadcom
Track: Tensilica Processors and Design IP
DIP201: Architecting the Most Advanced Automotive SoCs: Maximizing Safety and Performance
John Bainbridge, NetSpeed Systems
Track: Academic
ACA201: Application of Machine Learning to EDA Problems
Madhavan Swaminathan, Georgia Institute of Technology
Contact Us
Questions?
Email cdnlive@cadence.com
