CUS02 : Comprehensive, Consistent Power Intent Driven Low Power Methodology for Complex Mixed-Signal SoC

DAC 2017, Designer Track

Liran Kosovizer, Texas Instruments

CUS03 : EAD Usage for Rapid Design Convergence in SCD

Ernesto Kuznitzky, SCD

CUS05 : Analytical Design of Static Frequency Dividers and Ring Oscillators

Aleksey Dyskin, Technion

DSG02 : Leakage Reduction Using Tempus-ECO Solution

Asaf Oz, Altair Semiconductor

DSG03 : Innovus Flex-HTree Implementation for Block Level

Hila Lange, Marvell

DSG05 : Experience with Modus DFT and ATPG Solution for Achieving Automotive Chip Challenges

Idan Porat, Valens

IP01 : Millimetre-Wave Imaging Radar Applications

Ofer Familier, Vayyar Imaging

IP02 : Cadence Tensilica DNA 100 Processor

Lazaar Louis, Cadence

IP03 : Facial Recognition Demonstration on Vision C5 DSP/Protium S1 Platform

Cadence

IP04 : Cadence Interface IP Overview for the Enterprise Automotive and Consumer Segments

Ronen Laviv, Cadence

IP05 : Choosing Optimal DRAM Type to Meet Your Applications Memory Subsystem Needs

Shimon Raviv, Cadence

IP06 : Designing with Cadence High Speed SerDes

John Lupienski, Cadence

IP07 : High-Performance Interface IP for Advanced Datacenter

Muthukumar Vairavan, Cadence

IBV03 : A Methodology for Confirming the Safety of Reductions

Elchanan Rappaport, Veriest

IBV04 : Simplifying a Complex Verification Environment Using Specman Macros

Ron Sela, Valens

IBV05 : Developing a Random-Constraint Environment for the Resources-Allocation Problem

Yuval Adelstein, Hailo-Tech

SPB03 : Corning DRU Board Major Challenges and Impact of SI/PI Analysis During the Layout Phase

Alon Rozenvax, Corning Optical Communications Wireless

PCB03 : Manufacturing Yield in Mass Production

David Harlev, Kramer Electronics

PCB04 : Error Free Transfer Electronic Board from Design to Production

Yuval Givon, Innoviz Technologies

SVG02 : Pre-Silicon Verification of an Ethernet Packet Processor with Industrial Strength Traffic Generation

Gustavo Rodberg, Marvell

SVG03 : Using Palladium and Protium Platforms for Celeno 11ax WiFi Chipset

Ben Nahi, Celeno

SVG04 : PSS in Real Life

Julian Wurche, Texas Instruments

SVG05 : Latency-Constrained Design for a Display Stream Compression Decoder with Stratus HLS

Tim Papenfuss, Socionext Europe GmbH