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  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Integrity 3D-IC Platform
          • Cadence Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Voltus IC Power Integrity Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-XFi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • 112G/56G SerDes
          • Chiplet and D2D
          • Denali Memory Interface and Storage IP
          • Interface IP
          • PCIe and CXL
          • Tensilica Processor IP
        • RESOURCES
          • Discover PCIe
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • Multiphysics System Analysis
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Fidelity CFD
          • Sigrity Advanced SI
          • Celsius Advanced PTI
          • RESOURCES
          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
      • Embedded Software
      • PCB Design and Analysis
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • Allegro X Design Platform
          • RESOURCES
          • What's New in Allegro
          • Advanced PCB Design & Analysis Resources Hub
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        • Computational Fluid Dynamics
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Conference Proceedings

Custom IC and Analog

CUS02 : Comprehensive, Consistent Power Intent Driven Low Power Methodology for Complex Mixed-Signal SoC

DAC 2017, Designer Track

Liran Kosovizer, Texas Instruments

Download Slides

CUS03 : EAD Usage for Rapid Design Convergence in SCD

Ernesto Kuznitzky, SCD

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CUS05 : Analytical Design of Static Frequency Dividers and Ring Oscillators

Aleksey Dyskin, Technion

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Full-Flow Digital Design and Signoff

DSG02 : Leakage Reduction Using Tempus-ECO Solution

Asaf Oz, Altair Semiconductor

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DSG03 : Innovus Flex-HTree Implementation for Block Level

Hila Lange, Marvell

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DSG05 : Experience with Modus DFT and ATPG Solution for Achieving Automotive Chip Challenges

Idan Porat, Valens

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IP Solutions

IP01 : Millimetre-Wave Imaging Radar Applications

Ofer Familier, Vayyar Imaging

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IP02 : Cadence Tensilica DNA 100 Processor

Lazaar Louis, Cadence

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IP03 : Facial Recognition Demonstration on Vision C5 DSP/Protium S1 Platform

Cadence

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IP04 : Cadence Interface IP Overview for the Enterprise Automotive and Consumer Segments

Ronen Laviv, Cadence

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IP05 : Choosing Optimal DRAM Type to Meet Your Applications Memory Subsystem Needs

Shimon Raviv, Cadence

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IP06 : Designing with Cadence High Speed SerDes

John Lupienski, Cadence

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IP07 : High-Performance Interface IP for Advanced Datacenter

Muthukumar Vairavan, Cadence

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IP and Block Verification

IBV03 : A Methodology for Confirming the Safety of Reductions

Elchanan Rappaport, Veriest

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IBV04 : Simplifying a Complex Verification Environment Using Specman Macros

Ron Sela, Valens

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IBV05 : Developing a Random-Constraint Environment for the Resources-Allocation Problem

Yuval Adelstein, Hailo-Tech

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PCB Analysis

SPB03 : Corning DRU Board Major Challenges and Impact of SI/PI Analysis During the Layout Phase

Alon Rozenvax, Corning Optical Communications Wireless

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PCB Design

PCB03 : Manufacturing Yield in Mass Production

David Harlev, Kramer Electronics

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PCB04 : Error Free Transfer Electronic Board from Design to Production

Yuval Givon, Innoviz Technologies

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SoC and System Verification

SVG02 : Pre-Silicon Verification of an Ethernet Packet Processor with Industrial Strength Traffic Generation

Gustavo Rodberg, Marvell

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SVG03 : Using Palladium and Protium Platforms for Celeno 11ax WiFi Chipset

Ben Nahi, Celeno

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SVG04 : PSS in Real Life

Julian Wurche, Texas Instruments

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SVG05 : Latency-Constrained Design for a Display Stream Compression Decoder with Stratus HLS

Tim Papenfuss, Socionext Europe GmbH

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