ALT1 : Leakage Power Recovery for a Large AI Chip Using Tempus PBA Optimization

SadiqBeg Mirja, GLOBALFOUNDRIES
Anuradha Srikantaiah, GLOBALFOUNDRIES

ALT2 : Towards a Better UPF and CLP Verification Through Automation

Subhechcha Banerjee, GLOBALFOUNDRIES
Kushal Kamal, GLOBALFOUNDRIES
Wenxing Jia, GLOBALFOUNDRIES

ALT3 : Characterization of PCIe Gen4 SerDes (16GT/s) Using Sigrity and Best Layout Practices for PCIe Gen5 (32GT/s)

Prabhakaran Palaniappan, Mobiveil
Buvaneshwaran Chinnadurai, Mobiveil
Sreebharathi Chandrasekaran, Mobiveil
Jay Satishkumar, Cadence

ALT4 : Firmware Debugging Tracer in Palladium XP

Kubendra Kumbar, Samsung
Ken Joseph Kannampuzha, Samsung
Sandeep Vallabhaneni, Samsung

CI1 : Analog on Rails

Presentation Subject

Prashant Mathur, Intel
Likesh Sahoo, Intel

CI2 : Correct-by-Construction Layout Editing Using DRD In-Design Verification for Smart Power Technologies

Mona Joshi, STMicroelectronics
Livio Fratantonio, STMicroelectronics
Pankaj Rohilla, STMicroelectronics
Sachin Shrivastava, Cadence
Navit Rana, Cadence
Vishesh Kumar, Cadence

CI3 : Productivity and TAT Improvement Solutions for Analog Layouts in Advanced Nodes

Vinay A B, Avera Semi
Sandeep Torgal, Avera Semi
Pratik Vasant Korde, Cadence

CI4 : Virtuoso Design PlannerAn Effective Method of Planning, Estimating, and Implementing Hier Designs

Devendra Gupta, STMicroelectronics
Vishesh Kumar, Cadence
Monika Lilani, STMicroelectronics
Colin Thomson, Cadence

CI5 : Pattern-Based Routing for Custom Layout

Ravi Kumar Kallempudi, AMD
Rajesh R, AMD

CI6 : Managing Electrical Reliability During Layout Implementation

Atul Bhargava, STMicroelectronics
Akshita Mishra, STMicroelectronics
Devendra Gupta, STMicroelectronics
Rajeev Singh, STMicroelectronics
Sankalp Srivastava, Cadence
Vishesh Kumar, Cadence

CI7 : Configurable Stacked Decap Pcell Creation and Automated Placement at IP Level

Purushotham Ramakrishna, Avera Semi
Prashanthkumar Rajappa, Avera Semi
Vinay A B, Avera Semi
Vinutha Ramakrishna, Avera Semi

CI9 : Schematic Symbol PCell-Based Constraint Management for Voltage-Dependent Auto-Routing and Physical Verification

Amar Yadav, Samsung
Madhumitha Ramachandran, Samsung
Zinal Patel, Samsung

CV2 : A Methodology to Create Verification IP for Analog Modules

Neha Goel, NXP Semiconductors
Megha Chakrabarti, NXP Semiconductors
Chanda Thakur, Cadence

CV3 : Generation and Implementation Study of Moment-Based LVF Through Liberate and Tempus Technologies

Dileep Gangavaram, Invecas
Anil Babu Namala, Invecas
Ankit Saxena, Invecas
Ravi Kumar Kanala, Soctronics
Neha Garhwal, Cadence

CV4 : Addressing Semiconductor Reliability Challenges to Achieve Desired Yield Targets

Atul Bhargava, STMicroelectronics
Abhay Apte, Cadence

CV5 : Statistical EM Budgeting for Improved Reliability in FinFET Designs Using Voltus Technology

Soumyadip Adhikary, Sankalp Semiconductor
Priyanko Mitra, Sankalp Semiconductor

CV6 : Mixed-Signal Analysis and Verification to Meet ISO 26262 Safety Requirements

Chanakya K V, Texas Instruments
Jim Godwin,Texas Instruments
Samir Camdzic, Texas Instruments
Sumit Kumar, Texas Instruments
Vijay Kumar Sankaran, Cadence
Amit Bajaj, Cadence

CV7 : Black-Box EMIR: Hierarchical EMIR Approach for Improved Performance

Gaurav Dixit, Invecas
Bhanuprakash Raghavapuram, Cadence

CV8 : Improved Post Layout Simulation and Probing Methodology With Revamped Stimuli

Sunil Mehta, Intel
Itisha Chauhan, Intel

CV9 : PLL3GHz Characterization Using Liberate AMS Mixed-Signal Characterization

Santosh Narawade, Open-Silicon
Jithin Kumar, Open-Silicon
Rahul K, Open-Silicon

FED1 : Efficient and Fast Turnaround Name-Based Mapping for Multi-Bit Flops Using Conformal Technology

Praxal Shah, Google
Aishwarya Kumari, Cadence

FED2 : DFT Architecture and Methodology for Multiple Digital Islands in a Complex Mixed-Signal SoC

Nidhi U, Analog Devices
Kamatchi Saravanan, Analog Devices
Navdeep Sood, Cadence

FED3 : Smart Constraints and CDC Signoff with Conformal Litmus

Abdul Hameed, Invecas
Ravi Reddy, Invecas
Aishwarya Kumari, Cadence
Pankaj Khandelwal, Cadence

FED5 : Enabling Hierarchical FEF Flow for Quality Patch Generation with Runtime Benefits

Sidharth Ranjan Panda, Intel

FED6 : Abort Resolution with CUT Gates and Partition Points

Alok Mittal, NXP Semiconductors
Pankaj Khandelwal, Cadence

FED7 : Achieving Faster Turnaround-Time for Formal Verification for Multi-Million Gates Design

Sidharth Ranjan Panda, Intel

FED9 : Automated Memory BIST Methodology Using Genus and Modus Solutions for Configurable Tensilica Processors

Shantanu Velankar, Cadence
Ashlesha Karandikar, Cadence
Pallavi Mane, Cadence
Vidyut Patel, Cadence

FFS1 : Towards Early EM-IR Analysis for Robust Power Grid Design Using Voltus IC Power Integrity Solution

Suchibrata Das, GLOBALFOUNDRIES
Kushal Kamal, GLOBALFOUNDRIES
Raghavendra Jagalur, GLOBALFOUNDRIES

FFS2 : Improving Leakage and Dynamic Power of High-Performance Arm Cortex-A76 Core Using Cadence Solutions

Ashray Naik, Arm

FFS3 : Reduction in Number of Signoff PVTs During Power Domain Crossing Using Tempus Timing Signoff Solution

Pramod Gayakwad, NXP Semiconductors
Ramanath Dharmavaram, NXP Semiconductors
R Reshma Krishnakumar, NXP Semiconductors
Vasant Mundargi, NXP Semiconductors
Lakshmi Nair, NXP Semiconductors
Adarsh Chandranna, NXP Semiconductors

FFS4 : Case Study on Implementation and Timing Closure Challenges of a Design with 23B Gates and 625sqmm Area

Vishnuvardhan Nakka, Invecas
Ram Prasad Gopannagari, Invecas
Siva Naga Sankar Varudu, Invecas
Surya Narayana Varma Uppalapati, Invecas
Tirumala Srikanth Singari, Invecas

FFS5 : Methodology Abstracting Functional Behavior into Statistical Activity Framework for Automotive SoC

Abhishek Nigam, HCL Technologies
Rishabh Banerjee, HCL Technologies
Bhanu Prakash, HCL Technologies

FFS6 : An Insightful Journey of 7nm ASIC Tapeout Using Innovus-Tempus Solutions

Vismay Shah, eInfochips
Neha Shrotriy, eInfochips

FFS7 : Leakage Power Recovery with Minimal Timing Impact and Reduced Run-Time Using Tempus Timing Signoff Solution

Raghavendra Jagalur, GLOBALFOUNDRIES
Naveen Sampath Krishna, GLOBALFOUNDRIES
Kushal Kamal, GLOBALFOUNDRIES

FFS8 : MS-IR Signoff: Extending IR Analysis Beyond the Digital Using Voltus IC Power Integrity Solution

Shubha Rao, Analog Devices
Gavin Grant, Analog Devices
Shilpa Sathyanarayana, Analog Devices

DIG1 : Importance of Custom Clock Structures for High-Frequency CPUs

Shashank Pal, Samsung
Nagabharana Teeka, Samsung
Shymala BS, Cadence

DIG3 : Efficient Methodology for Smart Digital Power Grid Implementation of Automotive SoC

Abhishek Nigam, HCL Technologies

DIG5 : Low-Power Implementation of Crossbar Topology on Chip Interconnect Based on Tilelink Protocol

Jessita Joseph, CDAC
Deepu Krishnan, CDAC
Gopakumar G, CDAC

DIG6 : Power- and Performance-Optimized Implementation of a 14nm Low-Power DDR4

Mirunalini Gunasekaran, AveraSemi/GLOBALFOUNDRIES
Sandeep Patil HP, GLOBALFOUNDRIES
Nageshwara Danda, GLOBALFOUNDRIES

DIG7 : Integrating Blackbox Method in Flex-ILM and SAI-Based Hierarchical Flow for Faster TAT

Red 16x9

Rignesh Prajapati, Broadcom
Prashant Bhut, Broadcom
Navateja Mudalla, Cadence

DIG9 : 11LM FlexH Implementation for Hierarchical Blocks

Sandeep Patil HP, GLOBALFOUNDRIES
Santosh Surendra, GLOBALFOUNDRIES
Venkata Ramesh Etyala, GLOBALFOUNDRIES

PSBH1 : A Novel Approach for SoC Datapath Analysis Using Callback Functions of Verification Components

Balaji Viswanath Madhu, Samsung
Meghana Reddy Ganesina, Samsung

PSBH2 : A Novel Approach to Hunt for Bugs in an Algorithmic Design Exploiting Formal Verification

Tejbal Prasad, NXP Semiconductors
Navarshi Dhiman, NXP Semiconductors
Gaurav Gupta, NXP Semiconductors
Anshul Singhal, Cadence
Lokesh Sharma, Cadence

PSBH3 : Multi-Stage Pipelined Signal Modeling in Generic Processor Verification Using SV-UVM

Nirmal Suthar, eInfochips Ltd. (An Arrow Company)
Pranav Joshi, eInfochips Ltd. (An Arrow Company)

PSBH4 : Centralized and Automated Framework for Verification Management, Tracking, and to Address Required Traceability

Pranshu Agrawal, NXP Semiconductors
Jhalak Gupta, NXP Semiconductors
Tejbal Prasad, NXP Semiconductors
Anshul Singhal, Cadence

PSBH5 : Efficient Methodology for Design Verification Closure for Complex SoCs Using Save and Restore

Arushi Mittal, Samsung
Vasundhara Gupta, Samsung
Raghavendra Bindagere, Samsung
Somasunder Kattepura Sreenath, Samsung
Aishwarya Nadella, Cadence

PSBH7 : Verification of GDDR6 High-Speed Memory PHY IP Using Cadence VIP

Avinash Bharadwaj Narasimhaswamy, Rambus
Sampathkumar Ballary, Rambus
Dharini Subashchandran, Cadence
Rahil Jha, Cadence
Ramesh Gowd Kathi, Cadence
Vishnu Prasad K V, Cadence

PSBH8 : Bringing Discipline in RTL Increments

Rahul Iyer, Samsung
Jagannath Vishnuteja Desai, Samsung
Lokesh Sharma, Cadence

PSBH9 : NVMe Advanced Verification

Kamal Potta, Broadcom
Vinayak Halemani, Broadcom
Muralikrishna Juturu, Broadcom
Sangeeta Soni, Cadence

PCB1 : Reconnoitre Z-Direction EMC Pitfalls in PCB Designs

Amba Prasad, Tejas Networks

PCB2 : Achieving Smooth Manufacturing/High-Speed Signoff Using Real-Time In-Design DFM and Ravel Check

Ponraj Muthunadar, Sanmina SCI Technology

PCB5 : “First Time Right” for Manufacturing Release with Allegro Manufacturing Option

Meghna Khadikar, Mitsubishi Electric
Sneha Jadhav, Mitsubishi Electric

PCB6 : Rugged Circuit Design and Simulation Using OrCAD Capture CIS and OrCAD PSpice Advanced Analysis

Prathamesh Soman, Agiliad Technologies
Shriram Deopurkar, Agiliad Technologies

PCB7 : T2B IBIS Modeling for TSMC 7nm HBM4Gbps I/O Design

Santosh Narawade, Open-Silicon

PCB8 : Study of Routing Topologies for Complex Multi-Receiver Connectivity in PCBs

Ankita Sinha, ISRO
Shashikala V, ISRO

PCB9 : Budget Your Noise and EMC: A System Perspective Using Sigrity Technology

Anusha Murthy, Analog Devices
Bijaya Dash, Analog Devices
Claire Leveugle, Analog Devices
Jay Shah, Cadence
Sivaram Chillarige, Cadence
Ruchin Gupta, Cadence

AVM1 : Low Power Validation of Heterogeneous SoCs with Portable Stimulus Standard

Joydeep Maitra, Intel
Vikash Kumar Singh, Intel
Deepinder Singh Mohoora, Intel

AVM2 : Evolution of UPF and Its EDA Challenges on Non-Volatile Memory (eMRAM) IPs

Himani Jhajharia, Arm
Divyeshkumar Dhanjibhai Vora, Arm
Jeevan Jyoth Kumar Buddhi, Arm
Khushal Gelda, Arm

AVM3 : Perspec + ISequenceSpec = Spec to Validation Portability

Rajat Bagga, Agnisys Technology
Amanjyot Kaur, Agnisys Technology

AVM4 : Accelerating Multi-Layer System Verification with Verification IPs

Kannusamy Mariyappan, Samsung
Anshuman Mishra, Samsung

AVM5 : Comprehensive CDC Analysis and Verification Using JasperGold CDC App

Abhinav Parashar, Texas Instruments
Harish Maruthiyodan, Texas Instruments
Naveen Kothuri, Texas Instruments
Rupinjeet Marwah, Texas Instruments
Narendra Ravilla, Texas Instruments
Rajeev Suvarna,Texas Instruments

AVM7 : Unconventional Test-Bench Techniques for Mixed-Signal Low Power Verification - Beyond the Standards

DAC 2017, Designer Track

Lakshmanan Balasubramanian, Texas Instruments
Liran Kosovizer, Texas Instruments
Prachi Mishra, Texas Instruments
Sushmitha T G, Texas Instruments
Sunita Tirlapur,Texas Instruments
Manas Ranjan Raiguru, Cadence
Rewin Edwin, Cadence
Vijay Kumar Sankaran, Cadence

AVM8 : Improving Verification Productivity Using Dynamic Save/Restart and Test Methodology

Gaurav Kumar Yadav, Samsung
Vijay Kumar Birange, Cadence

AVM9 : Qualifying a High-Performance Memory Subsystem for ASIL-C Readiness for Automotive Applications

Pankaj Singh, Cadence

EMP1 : Challenges of Mixed-Signal Integrated Circuit Emulation

Pablo Cholbi Alenda, Analog Devices

EMP2 : Simulation Acceleration Using PCIe AVIP with RAL Support

Sathish Kumar Pitta, Broadcom
Jahangir Shaikh, Broadcom Vaishali Umredkar, Broadcom
Neeraj Sharma, Cadence

EMP3 : Enhancing IP DV: Constrained Random UVM TB Using HW Acceleration for Large Designs

Vivek Kumar, Samsung
Dishant Garg, Samsung
Chakravarthi Devakinanda Vurukutla, Samsung
Karthik Majeti, Samsung

EMP4 : Towards Secure and Safe Software Development Using Green Hills Software and Cadence Technology

Criss Tubbs, Green Hills Software

EMP5 : Verification Closure of a Data Processing Design with a 100X Helping Hand from Emulation

Sandeep Kumar Bojja, Analog Devices
Ameya Mulye, Analog Devices
Joydeep Bhattacharjee, Analog Devices
Ponnambalam Lakshmanan, Analog Devices
Anilkumar TS, Cadence

EMP6 : Shortening Design and Firmware Validation Timelines Through Reuse of UVM Simulation Testbench on Hardware

Vivek Kumar, Samsung
Divya Sri RK, Samsung
Mandar Mande, Samsung
Karthik Majeti, Samsung
Anilkumar TS, Cadence

EMP7 : HW-SW Communication Made Easy with SV-Connect for Arm GPUs

Pragati Mishra, Arm
Jitendra Aggarwal, Arm

EMP8 : Enhancing SoC Performance by Combining Simulator and Simulation Acceleration Flows

Ulka Sathe, Intel
Praveen M Venkata, Intel