- ALT1 : New Techniques in Allegro Technology to Improve High Speed Signal Quality
Surendhar M, L&T Technology Services
Sankaran M, L&T Technology Services
Kavitha E, L&T Technology Services
Poosanalakshmi G, L&T Technology Services - ALT2 : Best Fit Clock Tree Construction on High Performance and Extremely Complex Designs
Ranganadh V Mudumbai, Qualcomm
Uday S Mudigonda, Qualcomm
Abhinay Ponna, Qualcomm
Venkateswarlu P, Cadence - ALT3 : Automotive Imaging and Vision Challenges: MIPI CSI-2 Solutions
Kumar Rajeev Ranjan, Samsung
Anil Deshpande, Samsung
Vishnu Prasad, Cadence
Prachi Patil, Cadence - ALT4 : Functional Safety Derived from ISO 26262 for Non-Automotive Devices
Kashinath Handiganoor, Ignitarium
Pallavi Kulkarni, Ignitarium
Conference Proceedings
Alternate Presentations
Custom and Analog Design: Implementation
- CI1 : Custom Global Clock Tree Distribution: A Case for Automation Using SKILL Scripting Language
Mahesh Am, AMD
Prateek Mishra, AMD
Animesh Jain, AMD - CI2 : IC Technology Trends and Challenges with Unified Virtuoso Technology-Based Solutions for Advanced Nodes
Sandeep Torgal, GLOBALFOUNDRIES
Vinay AB, GLOBALFOUNDRIES
Pratik Korde, Cadence
Jonathan Fales, Cadence - CI3 : A Novel I/O Pad Cluster Development Methodology Using Cadence Design Framework II (DFII) Library Builder
Rajesh Mangalore Anand, AMD
Aniket Waghide, AMD
Girish A S, AMD
Jagadeesh AS, AMD - CI4 : Increased Productivity Solution for Full Custom Layout
Rajeev Singh, STMicroelectronics
Atul Bhargava, STMicroelectronics
Monika Lilani, STMicroelectronics
Shubham Gupta, STMicroelectronics
Komal Arora, STMicroelectronics
Vishesh Kumar, Cadence - CI5 : Automated Test Case Creation for Design Rule Deck Validation (DRDV)
Sharifsab Nadaf, Sankalp Semiconductor
Adarsh Kamkar, Sankalp Semiconductor - CI6 : Enhanced Layout Performance Using Virtuoso Suite for Electrically Aware Design (EAD)
Shashank Chaturvedi, STMicroelectronics
Shivam Kalla, STMicroelectronics
Vikas Rana, STMicroelectronics - CI7 : Methodology to Improve Analog Sub-System Layout Utilization
Anantha Kamath,Texas Instruments
Pavankumar Kulkarni, Texas Instruments - CI8 : Optimizing Analog Design for Layout Dependent Effects on 22FDX
Rajeev Singh, STMicroelectronics
Atul Bhargava, STMicroelectronics
Vishesh Kumar, Cadence
Michel Cote, Cadence - CI9 : Automatic Cut Metal Shapes Insertion in Advanced-Node Custom Design Process
Ankur Chaplot, Cadence
Sachin S, Cadence
Joyjeet Bose , Cadence
Pardeep Juneja, Cadence
Yashu Gupta, Cadence
Custom and Analog Design: Verification
- CV1 : Reliability/Aging Characterization for Standard Cells Using Liberate Characterization Solutions
Ankit Saxena, InVecas
Suresh Kanniyappa, InVecas
Atul Kumar Kashyap, InVecas - CV2 : Comprehensive, Consistent Power Intent Driven Low Power Methodology for Complex Mixed-Signal SoC
Lakshmanan Balasubramanian, Texas Instruments
Ramakrishnan Venkatraman, Texas Instruments
Aswani Kumar Golla, Texas Instruments
Nadeem Tehsildar, Texas Instruments
Manash Ranjan Raiguru, Cadence
Rewin Edwin, Cadence
Vijay Kumar Sankaran, Cadence - CV3 : Taking RNM Model to the Next Level: Power-Aware Verification of Mixed-Signal Designs
Subin Thykkoottathil, Analog Devices
Nagesh Ranganath, Analog Devices
Santosh Singh, Analog Devices
Jakub Dudek, Analog Devices
Nimay Shah, Analog Devices - CV4 : Overcome and Conquer the Current Day System Design Analysis Challenges Using Virtuoso System Design Platform
Jim Godwin R S, Texas Instruments
Chanakya K V, Texas Instruments - CV5 : Mixed Signal Verification of Advanced Data Converters
Vivek Tripathi, STMicroelectronics - CV6 : Verification of Mixed-Signal Hardware Safety Requirements Using a Novel MS Fault Injection Methodology
Sumit Kumar, Texas Instruments
Chanakya K V, Texas Instruments - CV7 : Creating Timing Models Including LVF with Moments for Accurate Timing Signoff
Savita Viswanath, Arm
Manigandeshwaran Mallikeswaran, Arm
Kartikay Sharma, Cadence
Shiva Raja, Cadence - CV8 : Techtorial: Using the New Virtuoso ADE and MATLAB Integration: A Practical Guide
Aniruddha Dayalu, MathWorks
Ashish Patni, Cadence - CV9 : Accelerating Electromigration and IR Drop Analysis with Spectre APS and Voltus-Fi Custom Power Integrity Solution
Lokesh Saini, Arm
Digital Front-End Design
- FED1 : SoC Level Power Estimation by Modelling Max Use or Specific Use Case Scenarios Using DV or AVV Test Cases
Saya Goud Langadi, Texas Instruments
Ranjitha H V, Texas Instruments
Sowmya Yadala, Cadence
Rahul Ramteke, Cadence
Ashwin Ramamurthy, Cadence - FED2 : Achieving Logical Equivalence Closure Through Conformal Smart LEC for Custom Mixed-Signal Designs
Krishnan Sukumar, AMD
Animesh Jain, AMD
Alexey Volosskiy, AMD
Animesh Sharma, AMD
Leyla Yilan, AMD - FED3 : Power Aware Synthesis
Venkataramanan Srinivasan, Cypress Semiconductors
Balamurugan M, Cypress Semiconductors
Mohit Gupta, Cadence - FED4 : Enhancing Test Compression to Next Dimension With 2D and Hierarchical Elastic Architectures
Kavithaa Rajagopalan, Texas Instruments
Aravinda Acharya, Texas Instruments
Wilson Pradeep, Texas Instruments - FED6 : Bridging Defect Coverage Gaps Using Cadence Modus DFT Software Solution Cell Aware ATPG Methodology for High Quality Test
Wilson Pradeep, Texas Instruments
Prakash Narayanan, Texas Instruments
Nischal Agarwal, Texas Instruments
Rajat Mehrotra, Texas Instruments - FED7 : Smart LEC--Next Generation Equivalence Checking Solution
Rajesh V, Cypress Semiconductors
Venkataramanan Srinivasan, Cypress Semiconductors
Mansi Singh, Cadence - FED8 : Speed Up Gate Simulations by Inferring Mapped Registers and Memories Using Conformal LEC
Rajesh GSVR, Broadcom
Aishwarya Kumari, Cadence - FED9 : PPA Improvement with Genus Synthesis Solution's Power Features for Low Power Designs
Siddharth Sarin, Texas Instruments
Tejas Salunkhe, Texas Instruments
Digital Full Flow and Signoff
- DSGFP : Featured Paper: Pushing the Performance Barrier on Arm Cortex-A76 on 7nm Technology Using Cadence Implementation Suite
Naga Yashas S, Arm
Deep Kanwar Bhullar, Arm - FFS2 : A Comprehensive Methodology for Low Power Implementations of Arm Cortex-A55 CPU Using Cadence Implementation Suite
Jaspreet Singh, Arm
Aronnya Basu, Arm - FFS3 : Resolving Timing Signoff Challenges for Large High Speed Networking ASIC Using Tempus Timing Signoff Solution's Scope Flow
Naveen Sampath Krishna, GLOBALFOUNDRIES
Parth Hetalbhai Lakhiya, GLOBALFOUNDRIES - FFS4 : Mixed-Signal STA: A Novel Methodology to Signoff in a Complex Mixed Signal SoC
Shwetha Basireddy, Analog Devices
Rajiv Nadig, Analog Devices
Karthik Sundararaj, Analog Devices
Prashanth Kumar, Analog Devices
Ankur Chavhan, Cadence - FFS5 : Accurate Activity-Based Power Estimation and Distribution for Vector-Less IR-Drop Analysis with Voltus IC Power Integrity Solution
Apurve Chawda, Texas Instruments
Shruti Kasetty, Texas Instruments
Subhadeep Ghosh, Texas Instruments
Saya Goud Langadi, Texas Instruments
MuraliMohan Thota, Texas Instruments - FFS6 : Accelerating the Timing Signoff for Large SoC Designs Leveraging Boundary Model in Tempus Timing Signoff Solution
Anushansha Kanoria, Mediatek
Rajeev Singh, MediaTek
Sai Phaneendra, MediaTek
Abhishek Goel, MediaTek
Niharika Gupta, Cadence
Arvind Veeravalli, Cadence
Mani Balusamy Radha, Cadence - FFS7 : Improved Signoff Glitch Analysis with Tempus Timing Signoff Solution
Saili Shete, Texas Instruments
Ajoy Mandal, Texas Instruments - FFS8 : Dynamic Voltage and Frequency Scaling Synthesis, Implementation and Signoff
Sathish Jajimoggala, Open-Silicon
Ramanjaneya Sai Kumar, Open-Silicon
Digital Implementation
- DIG1 : FinFETs: Challenges, Solutions, and Future Scope
Jagadeeshwar Surigi, GLOBALFOUNDRIES
Alok Chandra, GLOBALFOUNDRIES - DIG4 : Source Synchronous Interface Timing Challenges
Mayur Deshpande, Open-Silicon
Lokesswari M, Open-Silicon - DIG5 : PPA Strategies Using FDSOI Technology
Surya Narayana Varma Uppalapati, Invecas
Srikanth S T, Invecas
RamPrasad Gopannagari, Invecas - DIG6 : Multi Tap Clock Tree Based on Flex H-Tree Methodology in Innovus Implementation System
Deepu Paulose, Broadcom
Venu Merugu, Broadcom
Biki Gogoi, Broadcom
Sairaj Kiran Dharanikota, Broadcom
Srinivas Damarsingu, Broadcom - DIG8 : A Novel Approach to Achieve Ultra-Low Power on a High Frequency CPU Providing Premium User Experience
Madhur Jagota, Mediatek
Bhuvan RN, Mediatek
Arijit Hazra, Mediatek
PCB and IC Packaging Design
- PCB1 : DFX on the Fly
Amba Prasad, Tejas Networks - PCB2 : Design Capture Using SDA and EDM for Database Management
Ravikiran Vinayakamurthy, Western Digital
Shivkumar Agarwal, Western Digital - PCB3 : How to Efficiently Design and Optimize Stackup for Multi-Chip Packages
Akash Dang, SCL
Krishan Kumar, SCL
Shiva Prasad Jilla, Cadence - PCB4 : Effective Use of Design Partitioning to Reduce Lead Time
Mohamed Ummer, Wuerth Elektronik
Arun Muthukumar, Wuerth Elektronik - PCB5 : Advance Design Verification for SiP and PCB
Kameshvaran Muthusamy, Tessolve Semiconductor - PCB6 : Addressing SI Challenges and Analysis of PCIe Gen4 Systems
Arun Kumar, L&T Technology Services - PCB7 : Leveraging Virtuoso/ MATLAB and PSpice/Simulink Integration for AMS Product Development
Aniruddha Dayalu, MathWorks
Alok Tripathi, Cadence - PCB8 : Fast and Accurate System Model of DDR4 and Addressing the Challenges of Transition to DDR5
Prabhakaran Palaniappan, Mobiveil Technologies
Shanmugapriya Devadasan, Mobiveil Technologies
Buvaneshwaran Chinnadurai, Mobiveil Technologies
System Verification: Advanced Verification Methodology
- AVM2 : Safety FI Journey with Cadence’s Safety Solution
Rupinjeet Singh, Texas Instruments
Prashantkumar Sonavane, Texas Instruments - AVM3 : Accelerating SoC Integration Tests Using Perspec Portable Stimulus
Mahesh Tripathi, STMicroelectronics
Arun Kumar, STMicroelectronics - AVM5 : How to Use Indago ESW Debugger for Effective Software-Hardware Co-Debugging
Shoma Banerjee, Western Digital - AVM6 : Improving Verification Productivity Using Machine Learning
Ponnambalam Lakshmanan, Analog Devices
Rajarathinam Susaimanickam, Synapse Design Automation - AVM7 : Integration of vManager Metric-Driven Signoff Platform with Industry Standard "Doorsng" to Address Requirement Treacebilty
Aashish Mittal, NXP Semiconductors
Jitendra Kumar Khaddeo, NXP Semiconductors
Anshul Singhal, Cadence - AVM8 : Metric-Driven Verification Platform for DO254 Certification
Harish M, Cadence
Jeeri Rajasekhar Reddy, Cadence
System Verification: Formal
- FOR1 : Quick Way for RTL Cleanup Using JasperGold Superlint App
Vishal Jain, Samsung
Atrey Hosmane, Samsung
Rahul Harihara Iyer, Samsung
Pallavi Kuruvinashetty, Cadence - FOR2 : JasperGold LPV App Usage in Selection of SRPG Cells to Optimize Power and Area at SoC Implementation
Pramod Gayakwad, NXP Semiconductors
Ranjith Kumar Rengaraj, NXP Semiconductors
Veeresh Vijaykumar Sajjan, NXP Semiconductors
Pynda Dattatreya Gupta, Cadence - FOR3 : Complete CDC DV Approach
Abhinav Parashar, Texas Instruments
Harish Maruthiyodan, Texas Instruments
Gurram Madhushudhan Naidu, Texas Instruments - FOR4 : Verification Signoff with Metrics “Formal”ly
Pradeep Kumar Valipe, Xilinx
Harsh Vardhan Gupta, Xilinx
Vikram Kailasapu, Xilinx
Samratkumar Das, Cadence - FOR5 : Locally Asynchronous Design Verification
Sudhakar Surendran, Texas Instruments - FOR6 : Architectural Formal Verification of Coherency Manager
Soumit Biswas, NVIDIA - FOR7 : Formal Techniques for Optimizing the Fault Injection Analysis and Framework to Automate the Fault Injection Campaign
Ravindrareddy Pulicharla, Analog Devices
Pradeep Bagavathiappan, Cadence
Amod Khandekar, Cadence: - FOR8 : Formal Signoff with JasperGold Coverage - Demo
Saurabh Gupta, Cadence
System Verification: Hardware Assisted
- HW1 : Accelerating Driver Software and Improving Efficiency with Palladium XP Verification
Rajaravi Krishna Katta, Texas Instruments
Sudharsanan R, Texas Instruments
Naresh A, Texas Instruments - HW3 : Prototyping SoC Peripherals with Real Device Speeds on Protium FPGA-Based Prototyping Platform
Manoj Sharma, Xilinx
Kunal Varshney, Xilinx
Meera Bagdai, Xilinx - HW4 : Early Software Development for Safety and Security Modules in Real Time Microcontrollers
Sudharsanan R, Texas Instruments
Meghana Manavazhi, Texas Instruments - HW5 : Software-Driven Cache Coherency Verification Using Portable Stimulus on Palladium XP Emulation Platform
Gaurav Jain, NXP Semiconductors
Monika Tripathi, NXP Semiconductors - HW6 : Simulation Acceleration Using PCIe AVIPs
Praveen Maddu, Microchip
Oommen Thomas, Microchip
Neeraj Sharma, Cadence - HW7 : Protium S1: FPGA-Based Prototyping Made Easy
Anil TS, Cadence
System Verification: Performance
- PER1 : Accelerating Automotive Protocol Verification with UVM-e and Traceability with vManager Metric-Driven Signoff Platform
Mousumi Baruah, Bosch
Shafeek Ahmed Chittargi, Bosch - PER2 : Speeding-Up Simulations by Greater than 10X Using Xcelium Multi-Core
Sowmya Venkateswaran, Microchip
Renold Sam Vethamuthu, Microchip - PER3 : Automotive Ethernet: Future and Challenges in Auto
Ashish Saxena, NXP Semiconductors
Gaurav Jain, NXP Semiconductors - PER5 : Effective Way to Manage Regression Flow and False Toggle Analysis to Avoid Unwanted Power Consumption
Akhilesh Chandra Mishra, STMicroelectronics
Aditya KalpeshKumar Mehta, STMicroelectronics
Deepak Harod, STMicroelectronics
Anshul Singhal, Cadence - PER6 : Improving DFI Simulation Time Using Better Heuristics
Sriram Madavswamy, Analog Devices
Saranya Das, Analog Devices - PER7 : Advanced PCIe DV
Kotragoud HG, Samsung
Vinay Swargam, Samsung
Somasunder Sreenath, Samsung
Sangeeta Soni, Cadence - PER8 : Accurate Library Cell Modelling for Post-Synthesis LPS Using Xcelium Parallel Logic Simulation
Vireen Vodapall, Arm
Divyeshkumar Dhanjibhai Vora, Arm
Rewin Edwin, Cadence
