CDNLive India 2017

September 7-8, 2017
Bengaluru, India
Hotel Park Plaza
90-4, Outer Ring Road, Marathahalli, Bengaluru

CDNLive India 2017 brought together Cadence^® technology users, developers, and industry experts for two days of networking, sharing best practices on critical design and verification issues, and discovering new techniques for designing advanced silicon, SoCs, and systems.

Highlights of CDNLive India 2018

Presentations

This year’s conference featured more than 88 presentations from 10 different technical tracks, including a wide variety of user-authored presentations addressing all aspects of design and IP creation, integration, and verification. Designers discovered how others are using Cadence technologies and techniques to design silicon, SoCs, and systems efficiently and profitably.

Keynote Speakers

Jaswinder Ahuja (Corporate Vice President and India Managing Director, Cadence), Vinod Kariat (Vice President - R&D, Custom and PCB Group, Cadence), Venugopal Puvvada (Vice President - Engineering, Qualcomm), Oz Levia (Vice President - R&D, System Design & Verification Group, Cadence), and Dinakar Munagala (Co-Founder and CEO, ThinCi) each presented engaging, insightful talks on industry trends, challenges, and opportunities in electronic design.

Designer Expo

Nine exhibitors and four worldwide sponsors participated in the Designer Expo exhibition, and highlighted the collaborative ecosystem available to support you.

Best Presentation Awards

Congratulations to our CDNLive India 2017 Best Presentation Award Winners!

System to Signoff: Digital Implementation Track

Achieving “Sustainable” Performance (w/GHz) on Arm Core Using Advanced Methodologies and Cadence Tool
Priyanka Garg - Mediatek
Madhur Jagota - Mediatek

System to Signoff: Digital Front-End Track

Low Cost High Performance Built-In Self-Test Solution Using Cadence LBIST for Safety Critical SoCs
Wilson Pradeep - Texas Instruments
Aravinda Acharya - Texas Instruments
Naman Maheshwari - Texas Instruments

System to Signoff: Signoff and Power Analysis Track

Timing Optimization for a Better Signoff
Abhijit Pradeep - Microsemi
Abhishek Sampagavi - Microsemi

Custom and Analog Design: Implementation Track

Implementation of a pCell Feature Above the pCell Hierarchy Using ’Add-On pCell’ in SKILL, Virtuoso Solutions
Amar Yadav - NXP
Dwarka Prasad - NXP

Custom and Analog Design: Verification Track

Simulator Agnostic Techniques and AMS-XPS-MS Simulator for Faster System-Level AMS Co-Simulation
Lakshmanan Balasubramanian - Texas Instruments
Nadeem Tehsildar - Texas Instruments
Ramu Narthu - Texas Instruments
Bharath Kumar Poluri - Texas Instruments
Vijay Kumar Sankaran - Cadence
Badrinarayan Zanwar - Cadence

System Verification: Advanced Verification Methodology Track

Verification of Multi-Core Sub-System Using Perspec with Re-Usable Stimulus
Thiagarajan Ravishankar - Qualcomm

System Verification: Performance and Debug Track

FuSa DV: Looking for Holes in an ASIL ‘D’ Safety Concept
Shreya Dasgupta - Analog Devices
Ravindrareddy Pulicharla - Analog Devices
Akash Ganesan - Analog Devices
Vandana Dubbaka - Analog Devices
Nilkanth Pathak - Analog Devices

System Verification: Formal Track

Formal Verification for Analog/Mixed Signal Designs
Sudhakar Surendran - Texas Instruments

System Verification: Hardware Assisted Track

Combining UVM-Based Acceleration with In-Circuit Emulation for Thorough Validation Environment
Vinay Daglur - Broadcom
Praveen Tiwari - Cadence

PCB and IC Packaging Design Track

IBIS Plus Model Generation and Validation Using Sigrity-T2B for High-Speed IO Interface
Srinivasarao Kenguva -Qualcomm
Senthil Nagarathinam - Qualcomm
Shiva Prasad Jilla - Cadence