AC01 : Updated Cadence 2019 Portfolio Available for European Academics via Europaractice

Bryony Howard, STFC

AC02 : Lead Institution for Analog Design Automation: New Thoughts in EDA for Analog

Jürgen Scheible, Reutlingen University - Robert Bosch Center for Power Electronics

AC03 : IC Layout Automation with Self-Organized Wiring and Arrangement of Responsive Modules (SWARM)

Daniel Marolt, Reutlingen University

AC06 : PSS: Gearing Up for Large-Signal Simulation

Hannes Ramon, Ghent University - imec

AC07 : Application of Cell-Aware Test on an Advanced 3nm CMOS Standard-Cell Library

Zhan Gao, imec

AC08 : MEMS-IC Yield Optimization with Electrical and Mechanical Process Parameters

Florin Burcea, Technical University of Munich

AC10 : Formal Verification with Broad-Spectrum ANSI-C Reference Specifications

CREST C to Verilog based on CBMC

Thomas Melham, University of Oxford

AC11 : Master Thesis Contest Winner: Automated Design Space Exploration of Digital Audio Processors for Hearing Aids

Jens Karrenbauer, Leibniz Universität Hannover

AC12 : Synthesis and Test of IP Blocks with Fault Mitigation

Valentin Rozanov, SUAI
Elena Suvorova, SUAI
Yuriy Sheynin, SUAI

AC14 : Reliability, Security and Quality in Nanoelectronic Systems – Update from Cadence Early Stage Researchers

Felipe Augusto da Silva, Cadence
Ahmet Cagri Bagbaba, Cadence

ASIP02 : Addressing the State of Safety and Security in Today’s Autonomous Vehicles System Designs

Dan Mender, Green Hills Software

ASIP03 : A Configurable Fault-Tolerant Multicore System Based on Tensilica Fusion G3 DSPs

Markus Ulbricht, IHP

ASIP04 : A Tool to Ease Design-Space-Exploration Using the Tensilica LX7 ASIP

Florian Fricke, Ruhr-Universität Bochum

ASIP07 : Real-Time LED Flicker Mitigation on a Tensilica Vision DSP for Digital Side Mirror Systems

Nicolai Behmann, Institute of Microelectronic Systems, Leibniz University Hannover

ASIP08 : Mixed-Signal Analysis and Verification to Meet ISO 26262 Safety Requirements

Samir Camdzic, Texas Instruments

ASIP11 : CNN Design Space Exploration on Tensilica Vision P6 DSP

Nicolai Behmann, Institute of Microelectronic Systems, Leibniz University Hannover

ASIP12 : Multiframe Imaging on Tensilica Vision P6 DSP

Constantino Álvarez Casado, Visidon

ASIP13 : A 600 mV ULP Tensilica Fusion F1 DSP with Low-Voltage SRAMs

Joachim Rodrigues, Xenergic AB

ASIP14 : Case Study: Design Methodology for Optimized GPS IP Solution Using Tensilica DSP

Rabih Chrabieh, Nestwave

ASIP15 : Smart Hearing Aid Processor with Ultra-Low Power Consumption

Meinolf Blawat, Dream Chip Technologies

ASIP18 : Enabling High Performance-Computing Applications with Differentiated IP and Bleeding-Edge Semiconductor Processes

Adrian Danilescu, Samsung

CUS01 : PVS Voltage Aware DRC Using PVL Tcl DFM PROPERTY Advance Commands

Ofer Tamir, TowerJazz
Iryna Titarenko, TowerJazz

CUS02 : A New Methodology for Active Substrate Parasitic Extraction in Automotive HV-CMOS Processes

Klaus Heinrich, X-FAB Semiconductor Foundries GmbH

CUS03 : Precise Layout Area Estimation of Analog/Mixed-Signal Circuits

Dalibor Barri, STMicroelectronics
Patrik Vacula, STMicroelectronics
Vlastimil Kote, STMicroelectronics
Francesco Gaetano, STMicroelectronics
Jiri Behounek, STMicroelectronics
Jiri Jakovendo, Czech Technical University in Prague

CUS04 : Interactive Resistance Measurement for Hierarchical Layout Nets

Vladimir Slezkin, NXP
Laurent Le Cam, NXP

CUS05 : Design Intent - A Path Towards Better Communication Within IC Design Teams

Goeran Jerke, Robert Bosch GmbH
Vinko Marolt, Robert Bosch GmbH
Jaswant Rajpurohit, Robert Bosch GmbH
Detlev Funke, Robert Bosch GmbH
Tomas Geffke, Robert Bosch GmbH

CUS06 : Fast Design and Reuse of Analog IP Using Intelligent IP Generators and Virtuoso Environment

Benjamin Prautsch, Fraunhofer IIS/EAS

CUS07 : RF Simulation Techniques for Analog Circuits

Mohammed Aissi, Dialog Semiconductor

CUS08 : Optimizing Spectre APS Transient Speed and Convergence

Stephan Endraß, Texas Instruments

CUS09 : Verification of High-Level Design Requirements with Virtuoso ADE Verifier

Robert Kappel, ams AG

CUS10 : Implementing a Grid-Based Design Methodology to “Design Out” the Impact of Shrinking Nodes

Ciaran Whyte, IC Mask Design

CUS12 : Legato Reliability Fault Simulation - An Automotive Safety Case Study

Andrii Buzuluk, Melexis

CUS13 : Reliability Analysis Results Parsing Flow

Pei Yao, Xilinx
Jae-Gyung Ahn, Xilinx

CUS14 : Degradation Model Creation Flow

Roland Jancke, Fraunhofer Institute Integrierte Schaltungen
André Lange, Fraunhofer Institute Integrierte Schaltungen

DSG01 : The Challenge of Designing a “First-Time-Right” Wi-Fi HaLow Baseband in Less than Six Months

Stefan Stanic, Methods2Business

DSG02 : I2C PAD Characterization Methodology Using Liberate Characterization

Christopher Gleave, Dialog Semiconductor

DSG04 : LRTL-Based Power Calculation with Joules RTL Power Solution

Pierre-Emmanuel BERNARD, VSORA
Bertrand Genneret, VSORA

DSG05 : Conformal Smart LEC Results on ST ADG Devices

Antonio Lonigro, STMicroelectronics srl
Danilo Grassi, STMicroelectronics srl

DSG08 : M1 vs Poly Pitch: Gear Ratio Change

Giuliano Sisto, imec

DSG10 : Mixed Placer: An Unconventional Paradigm for Hard Macro-Intensive Designs

Lorenzo Arrigoni, STMicroelectronics

DSG11 : Designing a 7nm Multi-Core Arm Neoverse-N1 System on Chip Using Cadence Implementation Flow and IP

Stuart Riches, Arm

DSG12 : How to improve TAT and PPA by the use of Design Metrics

Daniel Kollar, Socionext Europe GmbH

DSG14 : A Flow for Early Power Analysis Using Joules and Voltus Solutions

John Gahan, Analog Devices

DSG15 : Die/Package Co-Design in 28FDOI Technology Using Voltus-Sigrity Package Analysis

Renato Castellan, STMicroelctronics

MS01 : Experiences in OpenAccess Interoperability with Virtuoso and Innovus Solutions for Mixed-Signal Designs

Birgit Klein, Infineon Technologies AG

MS02 : Fast Implementation of Small Digital Blocks Within a Custom Layout Environment

Damjan Vucic, ams AG

MS03 : Automated DfM Optimization Using Pattern Matching in Virtuoso and Innovus Solutions

Automated DfM Optimization Using Pattern Matching in Virtuoso and Innovus Solutions

Laurent Le Cam, NXP Semiconductors

MS04 : Design Flow and Technology Demonstrator for 60GHz WiGig Antenna Array on Package

Saquib Bin Halim, GLOBALFOUNDRIES
Christian Goetze, GLOBALFOUNDRIES
Marcel Wieland, GLOBALFOUNDRIES

MS07 : Visualize and Prevent EM Effects in Automotive Designs Using Voltus-Fi Custom Power Integrity Solutionation

Soumil Kumar, Melexis

MS08 : ASIC – Top Down Layout Flow

Alberto Gussoni, STMicroelectronics

MS09 : Real-Number Modeling of Loading Effects in Power Regulation using SV EEnet

Alvaro Caicedo, Texas Instruments

MS10 : UVM ATE Tester Probe UVC for Top-Level Mixed-Signal Verification

Juan Verdu, Texas Instruments
Martin Priess, Texas Instruments

MS11 : Chip-Level Verification of RF-AMS SoCs

Magnus Karlsson, Innowicom System Solutions AB

MS12 : Path-Based Timing Verification Flow for Full-Custom Circuits

Martin Schmidt, IBM

MS14 : Implementing Checks for Power Domain Crossings on Schematic Level

Stephan Henker, Racyics GmbH

MS15 : DARE SET Simulation Flow Integrated in Virtuoso Analog Design Environment

Staf Verhaegen, imec

SPB01 : Cross-Fabric Design Planning and Optimization, Taking Into Account the Package Routing Strategy

Cristina Somma, STMicroelectronics

SPB02 : Checking the Connectivity Between Design Fabrics

Renato Castellan, STMicroelectronics

SPB03 : Virtuoso Platform as a Common Layout Design Environment for Chip/Package/PCB Co-Design

Thomas Brandtner, Infineon Technologies Austria AG

PCB08 : Starrflex (Rigid Flex) Technologie

Andreas Schilpp, Würth Elektronik GmbH & Co. KG

PCB10 : Embedded Component Technology

Nicolas Faust, AT&S

SPB05 : Implementation of Complex Packaging Design Rules and Layout Optimization Using RAVEL Algorithms in Cadence SiP

Claire Laporte, STMicroelectronics

SPB06 : 25Gbps Simulations with Sigrity 2018 Release

Pepijn Kampf, Grass Valley

SPB07 : Electrical/Thermal Co-Simulation of SMPS High Current Density PCB Design

Radovan Vuletic, Infineon Technologies AG

SPB08 : SI/PI/EMC Full System Simulation of Complex Tester PCB Boards (40 layers) MLO, Contact Unit and IC (NXP Semiconductors)

Evert Janssen, NXP

SVG01 : Full-Chip System-on-Chip Verification Using Palladium Z1 Emulation Ecosystem

Sebastian Hesselbarth, Dream Chip Technologies GmbH

SVG02 : Hybrid Virtual + Emulation SoC Platform for SW-Drivers Validation

Shadi Barhoom, Intel-Mobileye
Rafael Zuralski, Intel-Mobileye
Gil Peled, Intel-Mobileye

SVG03 : Fast Processor Models for Software Bring-Up and Hardware-Software Co-Verification

Kevin McDermott, Imperas Software
Larry Lapides, Imperas Software

SVG04 : Dynamic Software Analysis in Virtual Platforms

Ola Dahl, Ericsson AB

SVG05 : SoC Architecture Validation and Exploration with SAVE

Raimar Thudt, Intel

SVG06 : PSS - Automotive Case Study

Leo Matturi, Infineon Technologies

SVG08 : TOP-Level Verification Challenges for Interconnect and Closing the Gap Using IWB/IVD

Nabil Abbas Hasoun, Ericsson AB
Rochdi Zouakri, Ericsson AB

SVG09 : Formal Verification Signoff for Digital IP: A Comparison Between Classical UVM vs Formal Based

David Vincenzoni, STMicroelectronics

SVG10 : A Comprehensive and Reusable Strategy to Verify Cores based on UVM and Formal Verification

Sara Bocchio, STMicroelectronics

SVG11 : Formal Verification in the Context of Highly Configurable IPs

Sebastian Lee Barrera, Texas Instruments
Martin Gut,Texas Instruments

SVG12 : Accelerate DFT Simulations with Xcelium Multi-Core Technology

Fabio Beretta, STMicroelectronics
Roberto Mattiuzzo, STMicroelectronics
Cosimo Torelli, STMicroelectronics

SVG13 : High-Level Synthesis Models in Pre-Silicon Verification

Rauf Salimi Khaligh, Intel Deutschland GmbH

SVG14 : Can Formal Solve Our Big Verification Problems?

Roger Sabbagh, Oski Technology, Inc.

SVG15 : A Python Client Library for vManager API

Niels Burkhardt, EXTOLL GmbH
Tobias Groschup, EXTOLL GmbH

SVG17 : Emulation Automation Workflow: Your Way to Success

Pranab Saharia, Arm

CL01 : Cadence Cloud / The Future of Electronic Design Automation

Jeff Critten, Cadence

CL02 : Cloud-Based Innovation for Semiconductor Design

Josef Waltl, Amazon Web Services