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  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Integrity 3D-IC Platform
          • Cadence Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Voltus IC Power Integrity Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
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          • Layout Design
          • Layout Verification
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          • Spectre X Simulator
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          • Virtuoso Layout Suite
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          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
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          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • 112G/56G SerDes
          • Chiplet and D2D
          • Denali Memory Interface and Storage IP
          • Interface IP
          • PCIe and CXL
          • Tensilica Processor IP
        • RESOURCES
          • Discover PCIe
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
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        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
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          • System Analysis Resources Hub
          • AWR Free Trial
      • Embedded Software
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        • PRODUCT CATEGORIES
          • Design Authoring
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          • Analog/Mixed-Signal Simulation
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          • Augmented Reality Lab Tools
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  • EMEA 2018

Conference Proceedings

Academic
  • Session AC01 : Updated Cadence 2018 Portfolio Available for European Academics via Europractice
    Bryony Howard, Science and Technology Facilities Council
  • Session AC02 : SW/HW System Co-Design Enablement for Coarse-Grain Heterogeneous Manycore Platforms
    Alexey Syschikov, Saint Petersburg State University of Aerospace Instrumentation
  • Session AC03 : Processor Architecture Tradeoffs for On-Site Electronics in Harsh Environment
    Stephan Nolting, Leibniz Universität Hannover
  • Session AC04 : Evaluation of Heterogeneous Tool Chains for Building Complex FPGA-Based MPSoCs
    Rizwan Tariq Syed, IHP Microelectronics
  • Session AC05 : Visual Programming Environment for Cadence SKILL
    Florian Leber, Reutlingen University
    Yannick Uhlmann, Reutlingen University
    Jürgen Scheible, Reutlingen University
  • Session AC06 : Design Flow Automation for On-Chip Inductors
    Stefan Kosnac, University of Heidelberg
  • Session AC07 : Impedance Matching Network Synthesis Toolbox for Cadence
    Aleksandr Vasjanov, Vilnius Gediminas Technical University
  • Session AC08 : Teaching Microelectronic Design by Doing
    Massimo Barbaro, Università degli Studi di Cagliari
  • Session AC10 : Embedded Toggle Generator to Provide Realistic Test Conditions During Test of Digital 2D-SoCs and 3D
    Leonidas Katselas, Aristotle University of Thessaloniki
  • Session AC11 : High-Level Design of Finite State Machines
    Niels Burkhardt, EXTOLL
  • Session AC12 : Cell-Aware Test: Significant Test Quality Improvement at Affordable Cost
    Zhan Gao, IMEC
  • Session AC13 : EDA Tools and Methodologies for High Quality Nanoelectronic Systems
    Felipe Augusto da Silva, Cadence
    Ahmet Cagri Bagbaba, Cadence
  • Session AC-Techtorial I : Creating a Parameterized Layout Module with Cadence PCell Designer
    Jürgen Scheible, Reutlingen University
    Florian Leber, Reutlingen University
  • Session AC-Techtorial II : Physical Implementation with Modgens
    Saul Rodriguez Duenas, KTH Royal Institute of Technology
    Johan Larsson, Cadence
Custom
  • Session CUS01 : Lifetime Verification by Circuit Level Aging Simulations
    Roland Jancke, Fraunhofer Institute
  • Session CUS02 : Case Study of Well Proximity Effects in 180nm
    Sorin Nedelcu, ams AG
  • Session CUS03 : Quantus FS and Advanced Technology PDKs
    Shanthi Siemes, GLOBALFOUNDRIES
  • Session CUS04 : Recent Enhancements in Quantus and its Integrated Capacitance Field Solver Allow New Applications
    Susanne Lachenmann, Infineon Technologies
    Petya Aleksandrova, Infineon Technologies
  • Session CUS05 : Constraint-Aware Simulation with ADE Checks/Asserts
    Volker Meyer zu Bexten, Infineon Technologies
    Markus Tristl, Infineon Technologies
    Paulo Tavares, Infineon Technologies
  • Session CUS06 : EM Check on Poly Resistor Device & RF FET Using Voltus-FI
    Shanthi Siemes, GLOBALFOUNDRIES
  • Session CUS07 : Virtuoso Layout Suite EAD. Beyond Aware…
    Goeran Jerke, Robert Bosch GmbH
  • Session CUS08 : Reducing ECO’s with Virtuoso EAD
    Rajeev Singh, STMicroelectronics
  • Session CUS09 : Automated P-Cell XOR with Instance Level Reporting
    Vladimir Slezkin, NXP Semiconductors
  • Session CUS10 : Common Design Migration Solution Through Universal Symbol P-Cell
    Vladimir Slezkin, NXP Semiconductors
    Sergey Yevstigneev, NXP Semiconductors
  • Session CUS12 : Device Level Design Implementation Methodology
    Rajeev Singh, STMicroelectronics
  • Session CUS13 : A Layout Methodology for Deep Sub-Micron Technologies
    Malcolm Gillett, Moortec Semiconductor
  • Session CUS14 : Prediction of RF Synthesizer Spurs Using Substrate Noise Analysis (QRC-SNA)
    Noel O'Riordan, S3 Semiconductors
    Eric Downy, S3 Semiconductors
  • Session CUS-Techtorial I : Analog IP Reuse & Process Migration: Challenges & An Innovative Methodology to Address Them
    Sowmyan Rajagopalan, Thalia
  • Session CUS-Techtorial II : Co-Simulation of Integrated Electronic and Photonic Circuits
    Greg Baethge, Lumerical
Mixed Signal and Advanced Methodologies
  • Session MS01 : Demystify the Mixed-Signal Simulation Errors
    Angelika Keppeler, Texas Instruments
  • Session MS02 : A Portable Environment for Mixed Signal Verification
    Sylvain Engels, STMicroelectronics
  • Session MS03 : An Efficient SKILL Based DB for Design Electrical Analysis
    Salvatore Santapa, STMicroelectronics
  • Session MS04 : XPS/Flash - A New Option for High Performance Flash Design Verification
    Marco Sommer, X-FAB Semiconductor Foundries
  • Session MS05 : A Flexible and Full Cadence Flow for Mixed Simulation
    Luca Tanduo, STMicroelectronics
  • Session MS06 : A Digital-Centric Real Number Modelling Based Mixed-Signal Design Flow
    Markus Mueller, EXTOLL
  • Session MS07 : Aspects of Library Characterization of Digital Standard Cells with Complex Circuit Topology
    Alexey Balashov, IHP Microelectronics
  • Session MS08 : System-Level Operating Condition Checks: Automated Augmentation of VerilogAMS Models
    Georg Gläser, IMMS
  • Session MS09 : Verifying Analog-Mixed-Signal Designs with Cadence’s Specification Driven Verification Tools
    Angelika Keppeler, Texas Instruments
    Juan Verdu, Texas Instruments
  • Session MS10 : Methodology for Spotting Floating Gate Induced Leakage Currents
    Peter de Vreede, Dialog Semiconductor
  • Session MS11 : Re-Use of a UVM Testbench in the Analog Simulation Environment
    Silvia Strähle, Infineon Technologies
    Rania Sanaa, Infineon Technologies
  • Session MS12 : Supply in a Multisupply Design: VerilogAMS Simulation Strategy for Multiple Supply Domains
    Yves Dufour, X-FAB Semiconductor Foundries
  • Session MS15 : Verification of Mixed-Signal HW Safety Requirements Using A Novel Mixed-signal Fault Injection Methodology
    Samir Camdzic, Texas Instruments
  • Session MS-Techtorial I : How to Create an Enterprise Design & IP Management Workflow for Engineers and Business Stakeholders
    Rado Prahov, Perforce
Full-Flow Digital Design and Signoff
  • Session DSG02 : Latency-Constrained Design for a Display Stream Compression Decoder with Stratus HLS
    Tim Papenfuss, Socionext
  • Session DSG03 : Inter-Module Matrix: A Metric-Driven Approach to Improving RTL Quality
    Jatin Mistry, Arm
  • Session DSG04 : RTL Stimuli Based Power Calculation with JOULES
    Johannes Bruecker, Renesas Electronics
  • Session DSG05 : Full Chip Power Signoff using the Voltus OnChip Voltage Regulator Flow
    Bertram Winter, ams AG
  • Session DSG07 : Conformal-ECO: How to Recover Six Weeks to PG
    Marcus Lindloff, Texas Instruments
  • Session DSG10 : Design Flow Development for Complex Designs in Advanced Technologies
    Erik Sander, Socionext
  • Session DSG11 : Integral RTL2Signoff Flow by Using Stylus for a Full Digital Flow Implementation
    Harald Hopperdietzel, Texas Instruments
  • Session DSG12 : New Optimization Strategies for High Performance CPUs Using GLOBALFOUNDRIES 22FDX Technology
    Jörg Winkler, GLOBALFOUNDRIES
    Ralf Flemming, GLOBALFOUNDRIES
  • Session DSG13 : Implementing a IoT Testchip and Software IP for the Arm Platform Security Architecture Using the Cadence Digital Flow
    Mike Eftimakis, Arm
SoC Design and Verification
  • Session SVG02 : A Deep Dynamic Formal Verification-Based Approach for Complex Systems-on-Chip
    Tomas Grimm, Ruhr-University Bochum
  • Session SVG04 : Augmented Reality and Rapid-Prototyping Based Supervision and Maintenance of an Industrial Process
    Florian Fricke, Ruhr-University Bochum
  • Session SVG05 : SRISA Protium S1 Approach
    Andrey Bogdanov, SRISA
    Alexander Kornilenko, SRISA
    Sergey Aryashev, SRISA
  • Session SVG07 : Improving Design Flow by Automating TLM Model Generation & Applying Existing RTL Based Verification
    Mohammed-Asif Qureshi, Renesas Electronics
    Horst Rieger, Renesas Electronics
  • Session SVG09 : Multi-Project, Multi-Site, Multi-Server: Deploying vManager in a Truly Global Organization
    Alan Whooley, Analog Devices
  • Session SVG10 : Automated Generation of Verification Charts Using vManager CS and Highchart Library
    Katarzyna Dukielska, Texas Instruments
    Michael Erdl, TUM
  • Session SVG11 : Clock Domain Crossing (CDC) and SuperLint: Two Mandatory JasperGold Apps for the Verification of IPs
    David Vincenzoni, STMicroelectronics
  • Session SVG12 : Delivering on the Promises of Portable Stimulus
    Mike Bartley, TVS
    Sharon Rosenberg, Cadence
  • Session SVG13 : PSS in Real Life
    Frank Donner, Texas Instruments
    Julian Wurche, Texas Instruments
    Filip Dojcinovic, Texas Instruments
  • Session SVG14 : Integration of "vManager" with Industry Standard “DOORsNG” to Address Requirement Treacebilty
    Thierry Nouguier, NXP Semiconductors
    Amina Zaibak, NXP Semiconductors
  • Session SVG15 : Vertical and Horizontal Code Reuse for SoC Functional Verification and Performance Analysis Stages
    Fedor Putrya, RnD Center «ELVEES», JSC
    Kirill Zhezlov, RnD Center «ELVEES», JSC
    Yaroslav Kolbasov, RnD Center «ELVEES», JSC
    Artyom Nikolaev, RnD Center «ELVEES», JSC
PCB Simulation
  • Session ICSIG01 : Application of Cadence Capture with PSpice as a Tool for Analog Circuit Diagnosis
    Elissaveta Gadjeva, Technical University of Sofia
Package and Board Design and Analysis
  • Session SPB02 : Application Driven Heterogeneous Integration
    Farhang Yazdani, BroadPak Corporation
  • Session SPB03 : Boost Automotive Co-Design Enhancement: A New SiP 17.2 Challenge
    Cristina Somma, STMicroelectronics
  • Session SPB05 : Allegro - Adopting a RTDFA Methodology
    David Burch, BAE Applied Intelligence
  • Session SPB06 : Layer Reduction and 30%+ SI improvement Using New Via Technology
    Joan Tourné, Nextgin Technology BV
  • Session SPB08 : Enabling System Electrical-Thermal Design
    Chris Aldham, Future Facilities
  • Session SPB10 : Temperature- and Geometry-Dependent Analysis of High-Speed PCB Traces
    Soumya De, Cisco
    Jian Liu, Cadence
  • Session SPB11 : PCIe 5.0 – Addressing the Simulation, Test, and Measurement Challenges of 32Gtps
    Tadeusz Asyngier, Tektronix
Automotive and IP Solutions
  • Session ASIP01 : Addressing IP Management and Traceability Challenges for ISO 26262
    Rado Prahov, Methodics
  • Session ASIP02 : Addressing PCIe Gen1-5 Test and Debug Challenges with Confidence
    Tadeusz Asyngier, Tektronix
  • Session ASIP05 : Enabling High Speed Interface IPs on Samsung Foundry 10LPP Process for Enterprise Applications
    Adrian Danilescu, Samsung
  • Session ASIP06 : An Area and Leakage Efficient Multi-Port SRAM for Near-Threshold Ghz Operation
    Joachim Rodrigues, Xenergic
  • Session ASIP07 : A 0.5V - 0.8V Tensilica Hifi Mini in 40nm LP
    Lauri Koskinen, Minima Processor
  • Session ASIP08 : Virtual Prototyping of Convolutional Neural Networks with Tensilica IP
    Fynn Schwiegelshohn, Ruhr-University Bochum
    Tomas Grimm, Ruhr-University Bochum
    Florian Fricke, Ruhr-University Bochum
    Florian Kaestner, Ruhr-University Bochum
    Michael Huebner, Ruhr-University Bochum
  • Session ASIP15 : Evolution of Next Generation Automotive ADAS SOC Design in 22nm FD-SOI Technology
    Young-Hun Kluge, Dream Chip Technologies
  • Session ASIP16 : Innovation in Cloud-Based EDA for IoT, AI, and Semiconductor Design
    David Pellerin, Amazon Web Services

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