Advanced Verification Methodology
Computational Fluid Dynamics
Custom and Analog Design: Implementation
Advanced Layout Migration Solution for Analog Designs
Atif Mohd, Intel
Sevanthy Gandhi, Intel
CADI1
Uncovering Parasitics Bottlenecks and Faster Design Closure with Early In-Design Parasitics Analysis Using Virtuoso EAD
Danish Shaikh, Western Digital
Sujit Swain, Western Digital
Narayana Hegde, Western Digital
Yashesh Kacha, Western Digital
Sana, Western Digital
Sethupathy Balakrishnan, Cadence
CADI10
An Effective Way to Identify the Routing Loops to Avoid Inductance Effects in Custom Layouts
Amit Biswas, Qualcomm
Debprasad Nandi, Qualcomm
CADI2
Application Readiness Checker (ARC) for Schematic-Driven Layout to Achieve 100% XL Compliance for Interoperability and Reusability of the Layout
Dhanesh Kumar Pragasam, Marvell
Sathish Rao, Marvell
Sandeep Torgal, Marvell
CADI3
Custom Device Place and Route Using APR
Vipin Kypada Chandran, Samsung
Prasanth K S, Samsung
CADI4
Electromigration-Aware Automatic Stacked Routing in Analog Layout Designs
Nisha Rana, STMicroelectronics
Rajeev Singh, STMicroelectronics
Akshita Bansal, Cadence
Sachin Bhasin, Cadence
CADI5
Mixed-Signal Implementation with Virtuoso Studio Layout Suite MXL Auto Place and Route Standard Cell
Urvashi Jindal, NXP
Manish Upadhyay, NXP
Akshita Bansal, Cadence
CADI6
Passive Components Synthesis and Analysis with EMX Designer for RF and mmWave Frequencies
Santosh Kumar Khyalia, ON Semiconductor
Basavaraj R Guttal, ON Semiconductor
CADI7
Quantus Insight to Analyze Interconnect Wiring Parasitics for High-Speed Circuits in Deep Sub-Micron FinFET
Kishan Chanumolu, Micron
Prateek Korde, Cadence
CADI8
Top-Level Guided Routing Using Design Intent Automation
Akansha Rai, Texas Instruments
Shanmuganarayan S, Texas Instruments
Chinna V, Texas Instruments
CADI9
Custom and Analog Design: Verification
Accelerating Monte-Carlo Simulations Using Statistical AI-Enabled Spectre FMC
Vignesh Balasundaram Sathiya Devi, STMicroelectronics
Atul Bhargava, STMicroelectronics
Badrinarayan Zanwar, Cadence
Prayes Jain, Cadence
CADV1
Spectre FX: Accelerating Circuit Simulation
Jim Godwin R S, Texas Instruments
Jerry Chang, Texas Instruments
Subbaraju Chintalapati, Texas Instruments
Yong Liu, Texas Instruments
Ian Woodburne, Texas Instruments
CADV10
Accurate Verification of High-Frequency PLL Designs Using Spectre-FX: New Era of Fast SPICE Simulation
Ankit Gupta, STMicroelectronics
Prayes Jain, Cadence
CADV2
AMS Debug Cycle Reduction
Kaustuv Sahu, Texas Instruments
Jim Godwin, Texas Instruments
Jerry Chang, Texas Instruments
Jackie Horn, Texas Instruments
Lalit Mohan, Cadence
CADV3
Analog Design Migration Across Different Technological Foundries
Debajit Kumar Das, NXP
Jaap Van Der Sluijs, NXP
Sony Manohar Dudhe, NXP
Sumit Patil, NXP
CADV4
Boost Productivity Working with Virtuoso ADE Verifier
Shreya Sinha, Texas Instruments
Keerthi Guntupalli, Texas Instruments
Angelika Keppeler, Texas Instruments
Walter Hartong, Cadence
CADV5
Effective Way of Power Leakage Analysis in Full-Chip AMS Simulation with Spectre FX Fast-SPICE Simulator
Pavan Vernekar, Infineon
Raghavendra Chavan, Infineon
Badri Zanwar, Cadence
Chao Feng, Cadence
Mohammed Shoaib, Cadence
Pradeep Marikundam, Infineon
CADV6
Effective, Predictable, and Faster Analysis at Full Chip SPICE level Using Spectre FX
Nitin Pant, NXP
Nimish Sharma, NXP
Vigyan Jain, NXP
Sudip Sarkar, Cadence
CADV7
Efficient Circuit Design Strategy Using Advanced Optimization Techniques
Mallikarjungouda Patil, Samsung
Mahesh Zanwar, Cadence
CADV8
Multimode PGV Generation and Validation
Sunil Suthar, NXP
Nisha Singh, NXP
CADV9
Digital Design Advancement with AI
A Novel Approach for Total Power Reduction in a High-Frequency Design with ML-based Cadence Cerebrus
Sarat Salihundam, AMD
Sabeesh Balagangadharan, AMD
Neeraj Dwivedi, AMD
Abhishek Guggari, AMD
Safrina Heera Mohammad, Cadence
Shyam Sundar A, Cadence
AI1
Accelerated CPU Design Closure Using AI-Based Cadence Cerebrus Reinforcement Learning in the Intel 18A Process
Sivaraman P, Intel
Anjaneyulu Bejawada, Intel
Yash Gaud, Intel
Manish Kumar, Intel
AI2
Achieving Best-in-Class PPA for High-Frequency Advanced Node CPUs Using Cadence Cerebrus Tool
Sagar Bhogela, Samsung
Ajay Vaddoriya, Samsung
Lokesh Jigalur, Cadence
AI3
Machine Learning-Driven PPA Optimization Using Cadence Cerebrus for OA-Based Mixed-Signal Designs
Aswani Kumar Golla, Texas Instruments
Kirtika Gupta, Texas Instruments
AI4
Digital Front-End Design and Test
Accelerating Logical Verification with RTL-PNR One PASS Flow
Amithanand Vk, Intel
DFDT1
Advancing Low-Power LBIST: Minimizing Power Consumption while Maintaining Test Time Standards
Jemin Mehta, Texas Instruments
Nitesh Mishra, Texas Instruments
Megha Mendu, Texas Instruments
DFDT2
Automated Abort Resolution Using Compare Recipes with SmartLec
Mallikarjuna Rao Bavanari, Qualcomm
Kiran Kumar M, Qualcomm
Hemanth Bollepalli, Qualcomm
Dheerajkumar Valivade, Cadence
G Gagana Sindhu, Cadence
Parul Bondwal, Cadence
DFDT3
Breaking Test Cost Barrier for Safety Critical Automotive Designs Targeting Zero DPPM
Nitesh Mishra, Texas Instruments
Rupesh Lad, Texas Instruments
Hrithik Sahni, Texas Instruments
Ravi Kumar, Texas Instruments
DFDT4
Cell-Aware Test Patterns to Reduce Test Escapes and Improve DPPM
Renold Sam Edward Alaises, Microchip
Saravanan Arulmozhi, Microchip
Navdeep Sood, Cadence
Shruthi Shekarappa, Cadence
DFDT5
Congestion-Aware Scan Chain Stitching Using Scan Groups Method
Tathagata Biswas, Google
Wilson Pradeep, Google
Vevek Gonugunta, Google
Shiva Thatipelli, Google
Mohan Kumar, Google
Vinay Shivakumar, Google
DFDT6
Evaluation of Elastic Compression Methodology Targeting Optimal DFT QoR
Parth Kadiya, Texas Instruments
Pervez Garg, Texas Instruments
DFDT7
Smart LEC: Logic Verification of Complex SoCs for Evolving Platform Devices
Sanjana Sundaresh, Texas Instruments
Likhita Maringanti, Cadence
Shanthala Nayak, Cadence
Arun Sivam, Cadence
DFDT8
UPF-Test Mutually Aware Test Insertion to Reduce Overall System Hibernate and Deep Sleep Power
Satya Bhamidipati, Infineon
Vandhana S, Infineon
Raghu G G, Infineon
Vijaya Astekar, Infineon
Ashwini Shankar, Cadence
Saroj Kumar Parida, Cadence
DFDT9
Digital Implementation
Achieving PPA Target for Intel's Highest-Speed CPU Designed at Intel's Latest Technology Node
Utpal Kumar Kar, Intel
Nitin Goyal, Intel
DI1
Challenges in Datacenters: Search for Advanced Power Management Mechanisms
Vijay N, ProteanTecs
DI2
Development of a Heterogeneous 3D Integration Flow with 3Dblox Using Integrity 3D-IC Platform
Mohammad Sameer, Intel
Srihari Vedula, Intel
Thillaiarasu Sakthi, Intel
Young Derick, Intel
DI3
Dynamic Methodology to Accelerate Power Structure Implementation Using FLASH PG
Rajat Sachdeva, NXP
Deepti Khurana, NXP
Anurag, Cadence
DI4
Innovus Glitch Power Optimization Using Joules Xreplay Flow
Tejas Bhalla, Broadcom
Vaibhav B P, Cadence
Sharad Bhushan Jha, Cadence
Anmol Khandelwal, Cadence
DI5
Minimizing Local Power Density Hotspots Using CDNS Native Flow
Sravanthi Gajjala, Intel
Rakesh Kumar, Intel
DI6
Model Margining Algorithm for High-Performance SOC Closure
Subhadeep Aich, Texas Instruments
Tejas Salunkhe, Texas Instruments
Siddharth Sarin, Texas Instruments
Gaurav Patil, Texas Instruments
DI7
Power Optimization for High-Speed SerDes IP in Advanced Nodes
Prasanna Kumar, Marvell
Mohammad Shoeb, Marvell
Karthik Raju, Marvell
Anup Kumar, Cadence
Akshay Mankotia, Cadence
DI8
Ultra-High-Frequency ARM CPU Implementation Using Cadence DDI Technology
Mohammedmuzaffar Ameerali, MediaTek
VijayKumar Vala, MediaTek
Santhosh Shanmukhappa, MediaTek
Manoj Mohan, MediaTek
Diljith P, Cadence
Bharath Gs, Cadence
DI9
Digital Signoff
"The Company you Keep" Impact of Local Layout on SoC
Aditya Mathur, Arm
DS1
Don’t Miss "MIS" - A Comparative Analysis of Timing Margining Methodologies for Simultaneous Input Switching
Shourya Shukla, Marvell
Prashant Shrivastava, Marvell
Swamy Lokanadham, Cadence
Nitin Jain, Cadence
Harshit Jaiswal, Cadence
Maddineni Yougandhar, Cadence
DS2
Early Scan IR Closure on SoC Through a Novel VCD-less Methodology
Somalatha T, Texas Instruments
Penchal Kumar Gajula, Texas Instruments
Prateek Giri, Texas Instruments
Mudasir Kawoosa, Texas Instruments
Siddharth Sarin, Texas Instruments
DS3
Efficient Rush Current Analysis for Power-Gated Designs
Abhinav Gaur, NXP
Akhilesh Mishra, NXP
Manoj Chahande, NXP
Ankur Chavhan, Cadence
Shaily, Cadence
DS4
Enhanced Performance Through Rapid Systematic Signoff Closure with Cadence Certus Closure Solution
Radhe Shyam Gupta, STMicroelectronics
Apoorv Garg, STMicroelectronics
Manish Tikyani, Cadence
DS5
Enhanced State-Propagation-Based Vectorless IR-Drop Analysis Emulating Realistic Silicon Behavior
Rishabh Singh, Texas Instruments
Subhadeep Ghosh, Texas Instruments
Ruchin Gupta, Cadence
Sushant Sharma, Cadence
DS6
Improving Design Performance with Pegasus PGFILL and Four-Plate Mimcap in Big Die Designs
Rishikanth Mekala, Samsung
Arpan Bhowmik, Samsung
Dhiraj Thalladi, Samsung
Anuradha Shankar, Samsung
Sailajaa Vidyadhari Kondapalli, Samsung
Abhishek Mahesh Chinchani, Samsung
DS7
Methodical ECO Strategies for Big Die SoC Convergence Using Tempus ECO Solutions
Tusharkant Mishra, Samsung
Pushpendra Yadav, Samsung
Damodaran Trikkadeeri, Samsung
Sahil Soneja, Samsung
Ranjith VR, Samsung
Nithyashree C, Samsung
DS8
Multi-Die STA for 2.5D Designs
Lakshmi Narayanan, Microchip
Bharathwaj T.A., Microchip
Anu Ramamurthy, Microchip
Akshay Mankotia, Cadence
Harshit Jaiswal, Cadence
Louis Lin, Cadence
DS9
Hardware and System Verification
Accelerating System Development Using Dynamic Duo, Palladium, and Protium
Ponnambalam Lakshmanan, Analog Devices
Ajeet Mall, Analog Devices
Ranjith Sankaranarayanan, Cadence
HSV1
Achieving Multi-Chip System-Level Coherency in the Early Phase of Design Using the "UCIe+CHI" Sub-System VIP
Murali S, Samsung
Sunil Shrirangrao Yellapragada, Samsung
Ashwini Pandey, Samsung
Anunay Bajaj, Cadence
Dimitry Pavlovsky, Cadence
HSV2
Automated and Scalable System Interconnect Verification Framework Using System Verification IP
Avinash Sanadhya, STMicroelectronics
Manvendra Singh, STMicroelectronics
Saurav Chatterjee, STMicroelectronics
HSV3
Emulation-Based Fault Campaign: The Pandora Box of Lightning Fast Safety Verification
Debasis Mishra, Samsung
Chandra Has Dondapati, Samsung
Prashantkumar Shukranath Sonavane, Samsung
Garima Srivastava, Samsung
Naveen Kumar V, Cadence
HSV4
Expediting Custom Core SOC Verification and Coverage-Driven Firmware Signoff Using ESWD and Indago Debug
Ayushi Bapna, Texas Instruments
Yogeshwaran Shanmugam, Texas Instruments
Arif Mohammed, Texas Instruments
Ashwini Padoor, Texas Instruments
Venkatesh Lingaiah, Cadence
Vinay Rawat, Cadence
HSV5
Left Shift of SoC Use Cases in Pre-Si Env Using a Common TB Across Simulation, Emulation (Palladium), and FPGA
Ashutosh Bisht, STMicroelectronics
Saurav Chatterjee, STMicroelectronics
HSV6
Performance Signoff and Report Metric Analysis of High Bandwidth Memories Using SYSVIP
Saravanakumar S, Samsung
Sekhar Dangudubiyyam, Samsung
Avit Gururaj Kori, Cadence
HSV7
Synthetic Traffic-Based Stress Test with Data Checker Integration and Performance Verification
T Chethan, Samsung
Anupam Kumar Singh, Samsung
HSV8
Unveiling Pre-Silicon Real-World System Benchmarking with PZ2_Insights into Performance Data and Silicon Correlation
Vinay Haritsa Prahallad Kardgur, Samsung
Milin K, Samsung
Sarang Kalbande, Samsung
Hyundon Kim, Samsung
Garima Srivastava, Samsung
HSV9
IP Characterization
Accurate CCS Power Characterization and Validation with Liberate Trio
Clinton Rodrigues, Samsung
Vedha S, Samsung
Haritsa C K, Samsung
Rajeela Deshpande, Samsung
Nitesh Verma, Samsung
Hariprasad R, Cadence
IP1
Modeling the Impact of Side Output Pins on Primary Arc in Multi-Output Cells
Subramanya Shindagikar, Arm
Phaniraj Jayatheertha Rao, Arm
Mohit Srivastava, Arm
Rajni Dhiman, Cadence
Harsh Gupta, Cadence
IP2
TCAM Characterization Using Cadence Liberate MX
Dan Lieberman, Marvell
Harsh Gupta, Cadence
Helen Shi, Cadence
Filzer Kummudiyil, Cadence
IP3
Unified Standard Cell Library Characterization Flow and Liberty Validation Framework Using ldbx Utility and Liberate LV.
Swapneel Biradar, GlobalFoundries
Kunal Goyal, GlobalFoundries
Gaurav Dhawan, Cadence
IP4
Utilizing Liberate MX Trio to Perform At-Speed Validations on Complex and Third-Party Memory IPs at STMicroelectronics
Shreyash Tripathi, STMicroelectronics
Anshul Garg, STMicroelectronics
Sachin Gulyani, STMicroelectronics
Swathi M N, Cadence
Dhanush J, Cadence
Gaurav Dhawan, Cadence
IP5
PCB & System Design and Analysis
10G Ethernet Compliance Post-Layout Validation Leveraging Clarity 3D Solver and AdvancedSI Sweep Manager
Naveen Sundaramurthy, Valeo
Venba Balakrishnan, Valeo
Harini Manoharan, Valeo
PCB1
Accelerating CAD Workflow Integration, Interpretation, and Optimization Using Sigrity Aurora
Harshitha S, Qualcomm
Ashwin Ramani, Qualcomm
Praveen Manikandan, Qualcomm
Sundhar Gurusamy, Qualcomm
PCB2
Analysis of DC Drop: PowerDC Tool Application in Advanced Packaging
Jagriti Jagriti, Intel
Anusha G V, Intel
PCB3
Constraints Setup Using Allegro Constraints Compiler
Kishore M, Qualcomm
Vinay Kumar Balumuru, Qualcomm
PCB4
Efficient Design and Verification of ATE Board Using Allegro System Capture
Pongiannan Gounder, Tessolve
PCB5
High-Speed Via and Channel Optimization to Mitigate Cross Talk and Frequency Domain Losses
Praveen Bhat, Achronix
Pratik Khurana, Achronix
PCB6
Leveraging AI in PCB Design Using Allegro X for Enhanced Productivity
Vanaruvi J, L&T Technology Services
Twinky H, L&T Technology Services
PCB7
Optimizing High-Speed Serial and Parallel Interfaces: Leveraging Sigrity AdvancedSI Sweep Manager for Best Tx and Rx Settings
Bharath Kumar, Hyundai Mobis
Ch S.V.S.S Upendra, Hyundai Mobis
Imran Shaik, Hyundai Mobis
Kweon Hyck Su, Hyundai Mobis
PCB8
Sigrity X Aurora Topology Extraction Workflow, and TopXp Workbench
Santhosh Rangasamy, Infineon
Ronak Desai, Infineon
Purshothama Rao, Infineon
PCB9
Performance and Smart Bug Hunting
3X Productivity Boost with Cadence Xcelium MC Solution
Tarun Goyal, NXP
Shivam Mittal, Cadence
Aman Kumar, Cadence
Shubham Srivastav, NXP
Bitu Singh, Cadence
PSBH1
Accelerating SoC Verification with AI-ML Flow
Narasimha Rao Chinni, Samsung
Sunil Shrirangrao Kashide, Samsung
Garima Srivastava, Samsung
Samar Singh Billawaria, Samsung
PSBH2
An Overview of Ethernet 10Base-T1S in Automotive SoC and its Verification
Asjad Fahmi, STMicroelectronics
Jagtar Singh, STMicroelectronics
Bipul Halder, STMicroelectronics
Sahana S, STMicroelectronics
Krunal Patel, Cadence
PSBH3
Efficient Test Failure Classification Using Auto Triage in Verisium Manager
Pooja Inamdar, Intel
Darrin Hancock, Intel
PSBH4
Ensuring Freedom From Interference for SEooC Automotive SoC Using SAC
Pattan Farooq Khan, Samsung
PSBH5
Leveraging Cadence VIP to Overcome Verification Challenges of PCIe-IDE in Automotive SoCs
Lopamudra Pattanayak, Samsung
Thanu Ganapathy Subramoniasarma, Samsung
Deep Mehta, Cadence
Garima Srivastav, Samsung
Sunil Shrirangrao Kashide, Samsung
PSBH6
Maximizing Verification Efficiency Using the Synergy of AI and Machine Learning
Amita Trisal, Qualcomm
Vivekananda Upadyaya P, Qualcomm
Ashwani Kumar, Qualcomm
Mayank Agarwal, Qualcomm
Parmar Rajdeep, Cadence
Sundararajan Ananthakrishnan, Cadence
PSBH7
Methodology for Faster Signoff of Gradational SOC Designs Using Jasper CDC and Superlint
Athavan Arasumani, Texas Instruments
Vijayalakshmi Kada, Texas Instruments
Tushar Puri, Cadence
PSBH8
Verification of Event/Performance Monitor of Coherent Interface with Cadence CHI b2b VIP
Vidushi Bajpai, Google
PSBH9