CadenceLIVE Taiwan – OnDemand

5G/RF, PCB Design and Packaging

The Key and Challenges to Designing mmWave Systems for 5G/B5G and SATCOM Communications

This presentation will show the key role of millimeter-wave and the reasoning of why millimeter-wave is required in modern communications such as mobile 5G/B5G and satellite communications. Some background theories of millimeter-wave and phased array antenna will be briefed. The challenges of millimeter-wave circuit and layout design will be presented and how Cadence’s simulation and layout tools play a key role in helping design engineers achieve their goal with accurate results. The presentation slides will also show how TMYTEK overcomes these challenges and what role TMYTEK play in the communication sector. Some application scenarios with regards to the solution of 5G/B5G and satellite communication systems will also be presented. Furthermore, some of the current standard TMYTEK’s products will also be introduced to help anyone who is interested in or want to get involved in millimeter-wave communication.

Su-Wei Chang, TMYTEK

Cadence and Dassault Systèmes Partner to Transform Electronic Systems Development

Cadence and Dassault Systèmes recently announced (2022) a strategic partnership to provide enterprise customers in multiple vertical markets, including high tech, transportation and mobility, industrial equipment, aerospace and defense, and healthcare, with integrated, next-generation solutions for the development of high-performance electronic systems.

The two companies have combined Dassault Systèmes’ 3DEXPERIENCE platform with the Cadence® Allegro® platform in a joint solution that enables companies to master the multidiscipline modeling, simulation, and optimization of complex, connected electronic systems. With this new multidisciplinary solution, customers can now accelerate their end-to-end system development process while optimizing their design for performance, reliability, manufacturability, supply resilience, compliance, and cost. Dassault Systèmes and Cadence have been engaged in a multi-year collaboration with leading customers to prove this solution in a global production environment.

The collaborative virtual twin experiences integrate capabilities for electronic and mechanical product lifecycle management, business process analytics and multidiscipline electronic systems development, engineering, and traceability. This holistic virtual model provides a complete, real-time view of electrical and mechanical simulation, manufacturing and supply chain execution for the product lifecycle, improving decision making, and accelerating innovation, through “what-if” studies.

Products and services are increasingly interconnected and intelligent, enabling consumers, citizens, and patients to unlock more personalized, engaging experiences that improve quality of life. In this dynamic context, companies must rapidly develop electronic systems that are safe, high quality, and right the first time. Mastering electronic system complexity and cost/time-to-market pressures requires collaborative innovation that unites electronics, mechanics, and additional functions across the value chain.

The presentation will discuss the strategic partnership between Cadence and that will revolutionize the development of high-performance electronic systems by enabling collaboration around virtual twin experiences.

Ben Lin, Dassault Systemes

Accelerating Allegro and Allegro Package Designer Plus by NVIDIA Virtual GPU Solutions

Cadence and NVIDIA partnership to utilize NVIDIA virtual GPU solutions in Allegro & APD Plus, gain performance over traditional OpenGL.

Andrew Liu, NVIDIA
Sungta Tsai, NVIDIA

Correlation between Measurement and Simulation of a 40GHz DTC (Deep Trench Capacitor) Test key with Cadence Clarity 3D Workbench

5G communication technology needs to support more and more high frequency bands which increases the number of RF passive components and spectrum. Deep Trench Capacitor (DTC) components with excellent characteristics and integration flexibility in wafer-level packaging have become one of the key components for high frequency 5G communication applications. In this paper, we demonstrate a 40GHz DTC verification flow to ensure the correlation between measurement and simulation based on Cadence Clarity 3D Workbench.

In order to ensure the correlation, first, we need to design a 40GHz wide bandwidth (BW) test coupon constructed with grounded coplanar waveguide (GCPWG) combined with two wide BW connectors for S21 measurement using VNA to confirm this test vehicle performance and measurement environment suitable to operating at 40GHz BW condition. Then, we assemble the DTC into the test coupon to measure this DTC intrinsic characteristic. 

Moreover, based on Cadence Clarity 3D Workbench, we would like to build up a replica environment in order to capture all of the physical phenomena same as measurement environment. 

According to simulation result, finally, we successfully capture the notch response of insertion loss S21 at roughly 38 GHz caused by physical PCB manufacture combined with connector assembly. Therefore, Clarity 3D Workbench indeed shows a perfect correlation with measurement for high-frequency and high BW analysis.

Bowei Chen, ITRI

SI, PI, EMI Designs, Simulations

Signal integrity (SI) and power integrity (PI) are essential for high-speed system design. Complete signal and power integrity design will also reduce the effects of electromagnetic interference (EMI). Cost-effective channel designs, such as using the leadframe packages instead of BGA packages, the wirebonding packages instead of flip-chip packages, or the 2-layer PCB instead of 4-layer PCB, are the demand for the consumer electronic applications. However, the channel integrity challenges including SI, PI, and EMI would be suffered if the careful design and simulation were not taken. Like the silicon intellectual property (SIP) in semiconductors, a package design that was verified by simulation or measurement to solve SI, PI, or EMI problems would be the package intellectual property (PIP). Similarly, a board and a channel design verified by simulation or measurement to solve SI, PI, or EMI problems would be the board intellectual property (BIP) and the channel intellectual property (CIP), respectively. Those intellectual properties can be reused in the high-speed system design and could be applied for invention patents. In this presentation, thirty-three (33) US awarded patents are classified into PIP, BIP, and CIP. Their SI, PI, or EMI problems occurred in the packages, boards, or channels and investigated with simulations or measurements will be demonstrated. Reuse of PIP, BIP, and CIP is encouraged that would ensure the system performance and achieve faster time to market.

Nansen Chen, MediaTek

Accelerating PCB Design Cycle with Allegro 17.4 New Features

This presentation will introduce near new feature in Allegro PCB Editor 17.4, including online manufacturability check, PCB layout with enhanced high-speed routing structures functionality, and enhanced allegro constraint compiler, etc. These features can provide user more flexible and more useful operation when faced with different design situation.

Natasha Hsieh, Cadence

Cloud & IP

Best practice for running EDA tools on Microsoft Azure

Leveraging purpose-built cloud infrastructure for EDA simulation to cut down time to market, whereas optimize TCO, increase throughput and Security has become mainstream in global market. In this session we will walk through the latest offering for the EDA building blocks on Azure, business/technical benefit, valuation criteria as well as best practice for running Cadence Spectre X/xCelium/Tempus.

Raymond Tsai, Microsoft Azure
Jacob Hsiao, Microsoft Azure

Run EDA Workloads on Google Cloud - Best Practices and Optimizations

Running EDA jobs on Cloud can be different from on-premises, since it’s possible to run your workloads with the various solutions on Cloud to gain agility, flexibility and productivity. This presentation highlights the best practices and options to optimize EDA workloads on Google Cloud.

Wayne Lin, Google

Pegasus TrueCloud for Giga-Scale Physical Verification Using Hybrid Cloud on Amazon Web Services

Historically, physical verification jobs have been very compute- and memory-intensive. Silicon designers are often resource-challenged to run physical verification on designs that can consume 1000s of CPU cores and require multiple days to complete. The new Pegasus TrueCloud enables designers to run physical verification jobs from on-prem compute resources onto the cloud and has a massively scalable architecture that can reduce design cycle time.

Attila Lin, AWS

5X Faster Library Characterization in Cloud

Library characterization for an advanced node design is a compute-intensive task -- ideal for a scalable and flexible cloud. In this presentation, M31 will describe a Library characterization methodology that enabled 5x faster delivery using Liberate on Cadence-managed CloudBurst.

Scott Li, Cadence

Cadence/M31 IP Solution for Memory and SerDes Interfaces

Cadence/M31 IP Solution for Memory and SerDes Interfaces

Stanley Huang, Cadence
Jerome Hung, M31

Designing the Next Ultra-Low-Power Always-On Solution

Designing the Next Ultra-Low-Power Always-On Solution


Custom/Analog and Mixed Signal Design

Accelerate Power Integrity Signoff with Voltus -XFi Solution

The Cadence Voltus-XFi Custom Power Integrity Solution is a transistor-level electromigration and IR drop (EM-IR) tool that delivers foundry-supported SPICE-level accuracy for power integrity signoff. EM-IR presents unique challenges at the transistor level, from complex EM rules to the high costs of simulating for current on a large RC network at post-layout. Enabled via an integration with the Cadence Spectre X SPICE Simulator and the Virtuoso Design Platform, the Voltus-XFi solution accelerates power signoff analysis and closure.

Robert Lin, Cadence

Evaluation of Next Generation Fast SPICE Simulator - Spectre FX

In this evaluation, Spectre FX simulates three designs, DDR, PCIE, and PMIC regarding pre-layout, post-layout and mixed-mode simulations respectively. The performance shows 10X+ faster compared to golden runs of Spectre X without accuracy lost.

CGE, Phison

How to Use Cadence Tools To Accelerate the Design Flow
This speech will introduce which products and processes M31 uses cadence flow, how to use cadence tool with in house developed flow to accelerate the efficiency of reliability verification and inspection, and how to improve the mass production efficiency of products.

Chan-Liang Wu, M31

Advancing design and verification of Mixed-Signal Systems through Cadence Virtuoso ADE - MATLAB/Simulink Integration workflows

The challenges of today's advanced silicon process nodes, as well as stringent performance targets, escalate mixed-signal design complexity. As these designs are created in different abstractions and design flows, exhaustive verification routines are needed to ensure the consistency in functionality and compliance to specifications. In this presentation, MathWorks will present the latest advances in the integrated MATLAB and Virtuoso ADE workflow for data visualization and analysis through the new Mixed-Signal Analyzer (MSA) app to enable seamless data post-processing. We will use a peaking filter/CTLE as an example to demonstrate how we can bring data from Virtuoso in MATLAB, perform a custom analysis such as a rational fit of the peaking filter/CTLE model in the MSA app, generate VerilogA models of the same and bring these models back into Virtuoso to complete a round-trip workflow.

Phoebe Li, Terasoft

Machine Learning and Digital Flow

Mediatek Enable Cerebrus AI for Next Generation Mobile CPU

CPU plays a very important role in high performance computing design. Performance, Power, and Area (PPA) all need to push to the design limit. But with the challenging schedule, we don’t have enough time to complete all experiments, and may miss good flow options due to lack of results analysis. Cerebrus AI helps user easy and quickly generate optimal flow reducing time and resources and find solutions human engineers might not naturally try/explore. MediaTek and Cadence close collaboration makes Cerebrus land on production chips and gain great success on CPU PPA improvement.

Ryan Tseng, MediaTek

Enable Cerebrus ML Optimization to Push Performance for Next Generation 3nm Infrastructure CPU

Global infrastructure is changing rapidly to accommodate growing workloads and increasing performance demands. Arm Neoverse CPUs deliver the speed and energy efficiency needed for the latest infrastructure requirements. As part of designing the next generation Neoverse CPUs, Arm manually develop and fine tune optimized Cadence digital full flow to deliver the aggressive performance and power goals. For the latest 3nm Neoverse CPU, Arm enabled Cadence Cerebrus ML flow optimization which automates the whole process, resulting in better PPA with much less Arm engineering effort. Join this session to learn how Arm are benefiting from automated Cerebrus ML flow optimization for next generation infrastructure CPUs

Talent Chang, Cadence

AI Acceleration and Optimization with High-Level Synthesis

We are developing a better acceleration design to compute AI algorithms very fast and consume the least resources to fulfill the growing computational complexity of deep learning. As AI models keep evolving rapidly, high-level synthesis allows designers to evaluate the trade-off between performance and resource overhead quickly, and evaluate a variety of microarchitectures at a higher design level, considering the software and hardware integration. As the architecture scales up, there are crucial challenges to exploring the optimized acceleration architecture. We will also share our experiences using high-level synthesis in a human-like robotic arm with intelligent control. Our design platform optimizes the trajectory control of the robot arm with a very efficient hardware architecture. The evaluation can be done in an integrated cyber-physical system of a robot simulator and an electronic system-level platform.

Chih-Tsun Huang, National Tsing Hua University

Voltus Flow Enhancement in SoC-ImP

In advanced technology, there are a lot of design issues that need to be solved. At the same time, the power impact is getting more emphasized. Compared to previous generations, the problems of IR drop and EM are becoming more serious. Thus, the accuracy of power simulation directly decides the directions and decisions of physical designs. Considering product competitiveness, we need to get the best results at the shortest amount of time in physical design. From the description above, we know that getting the data completeness in the shortest amount of time for the power analysis are the critical factors in the success of physical designs.

To effectively perform each project and preserve the design experience, especially considering the convergence of the complexity of advanced technology process data and its completeness, Socle has established a through SoC-Imp environment to ensure all the process data are properly set up. Since it’s done automatically, it drastically reduces human resource waste and assure of the accuracy and completeness of the environment and the physical design thoroughness.

Since the major industrial power evaluation tool and physical design tool are Voltus from Cadence, and Innovus, also, from Cadence, respectively. To have more direct design logic for power analysis, we choose Voltus for power analysis, and have integrated Voltus into SoC-ImP to elevate its performance to make sure of the design data completeness and provide an automatic process for each project. Power analysis can be done more efficiently. With more realistic simulation results, it effectively converge the complexity of advanced technology and has the more efficient and smooth physical design process.

Frank Wu, Socle

3D Partitioning and Placement for Next Generation 3D-ICs with Integrity 3D-IC

Multi-chiplet design and packaging introduces extra design and analysis requirements like system planning, TSV and Micro-bump insertion, extraction, electrothermal analysis, cross-die STA, and inter-die physical verification . A brief introduction to Cadence® Integrity™ 3D-IC platform will be presented which integrates planning, implementation and analysis to address the new requirements of 3D-IC design and signoff for different packaging styles.

Thunder Lay, Cadence

System Design and Analysis

Challenges of NAND Packaging for Capacity & Bandwidth Scaling

Challenges of NAND Packaging for Capacity & Bandwidth Scaling

Julien Su, MXIC

Signal/Power Integrity Challenge in Next-Generation Data Center

5G brings so much data transfer while leading industrial transformation. Not only the user devices need to be upgraded, but equipment in data center have to afford more loading and provide faster data transfer which means higher electrical data rate is considered. In recent three years, with 4-level pulse amplitude modulation (PAM4) has been had high confidence in 50G SerDes/lane and stronger techniques in equalization, it will also be applied to 100G and even future 200G. Meanwhile, big power consumption accompanies because more tap of TXFIR, more stage of CTLE, DFE and FFE. Those high-end equalization induce much power and make network switch system power consumption go to 3000W. Fortunately, we can take the benefit from system in package or system integration technology for relaxing equalizer while reducing power consumption and thermal loading.

Jerry Hsu, Wistron

High-Speed SerDes Simulation in Package Design by Using Cadence Clarity 3D Solver

In the package design stage, more accurate and fast simulations are important.

How to simulate and analyze more and more differential signal pairs on package at short notice? Cadence Clarity 3D can provide the accurate results efficiently in limited hardware resources. Furthermore, we can use the flexible settings in Clarity 3D to approach the package design.

Lance Hsu, Realtek

Cadence Optimality Intelligent System Explorer

The Cadence Optimality Intelligent System Explorer is multiphysics optimization software, enabling multidisciplinary analysis and optimization (MDAO) realization of electronic systems. With the increasing complexity of electronic system design and greater performance requirements, Optimality Explorer breaks through the limitations of the conventional human-intensive process by delivering a simulation and analysis workflow that results in the optimal design fast and efficiently. By replacing a traditional interactive flow of design, test, and refine loop, Optimality Explorer, with its artificial intelligence (AI)-driven MDAO technology, results in the optimal system design solution expeditiously and without compromising accuracy.

Bill Hung, Cadence

Consider Multiphysics of Co-Simulation in Advanced Package and PCB Design Using Celsius Thermal

Thermal management of electronics becomes more critical and complex when resistive losses in PCB and package structures are significant. These resistive losses are also temperature dependent, making electrothermal co-simulation necessary for such designs. In this presentation, we will look at using Celsius for thermal and electrothermal analyses at the PCB level. We will also look at how such designs can be simulated within electronics systems, to capture important system effects (such as airflow within an enclosure) and cooling mechanisms (such as heatsinks and fans).

Mason Chang, Cadence


Full Flow Verification From IP, SoC to System

Phison is the market leader in NAND Flash controllers and applications including USB, SD, eMMC, PATA, SATA, PCIe and UFS. To fulfill the various design requirements and get state-of-arts SOC in advanced process nodes, the design verification becomes one of biggest challenges for chip success and 1st-cut work. Also, in order to get products in time to market, the verification throughput and efficiency are major focus and attentions to improve further.

Cadence verification full flow comprises holistic solution and technologies to achieve and overcome the goal from different angles and realize 

• High Performance & Verification Regression Throughput

• Smart Debug

• Verification IP for New protocols on Phison SOC & IP designs

In this presentation, it will showcase Cadence verification full flow in real Phison SOC projects.

Racer Yang, Phison

Shift left with Helium for Modern SoC Development

To achieve earlier software engagement for AI/HPC SoC development and validation, GUC proposes a flow to deploy virtual platform into design and verification flow. With this platform, DV team and Software team can exercise application development and software flow in very early stage of project execution. Such that project team can locate/respond architecture flaws and software bugs in timely manner which great contribute to project success.

Philip Tsai, GUC

Security Concerns in AI Designs
Two security issues of AI designs will be discussed in this talk. One is about data leakage, especially how to guarantee that the well trained parameters will not be leaked out of the AI accelerator designs by formal verification. The other topic is to discuss the robustness of neural network designs, including what robustness problem is, when we should pay attention to this issue, and how to estimate it with different approaches.

Yean-Ru Chen, NCKU

Accelerate MCU Verification - Experience with Palladium Emulation Platform

As the world’s leading MCU vendor, Nuvoton provides rich product portfolio from 8051, Cortex-M0/ M23/ M4 to Arm9-based microcontroller, offering numerous parts for selection. In order to develop products with high quality, Nuvoton is always working on improving the verification flow. In this presentation, the speaker will share how Nuvoton leverage Palladium to address the limitation of current verification flow with its huge capacity and rich physical target interfaces. The debugging cycle also get reduced with the help of the strong debugging capability provided by Palladium.

Chi-Chuang Hsu, Nuvoton

Verification AI at Xcelium ML – Faster Coverage Closure
Coverage closure is the TPO signoff criteria for modern ASICs. Design team and Verification teams both took lots of time and effort to reach the coverage goal, and looking for better methodologies and solutions. Randomization of test patterns improves the efficiency of producing many sequences to a design under test. It is especially effective for stressing the design with scenarios that are hard for a human to create directly. While this sounds attractive, it inevitably reduces the understanding of what is going on in the simulation of your tests, which could become problematic when you compose a regression from these tests. A basic question, such as “How many random seeds should be assigned to each test?”, is hard to answer. By extracting knowledge from regression data using machine learning and capturing that knowledge in statistical models. The novel ML capabilities of simulator can help to reach the coverage goal faster and with shorter time.

YJ Chen, Realtek