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Automotive Solution and IP

Cadence Holistic Function Safety Flow for Automotive-Based on “Midas” Platform

Li Wan, Cadence

Using Xcelium Apps for Fault Simulation

Kelong Xu, Cadence

基于仿真平台的系统验证

Xiaoli Hu, Autochips

Accelerating Successful Designs with Cadence IP, from HPC, AI/ML to Auto/Mobile/Consumer Applications

Arno Li, Cadence

IP Solutions Targeting a Broad Range From Sensing to On-Device AI for Automotive Market Needs

Wei Wang, Cadence

Arkamys Sound Stage Solution, A Successful Audio Product Using Hifi DSPs for Automotive Infotainment System

Xuedan Zhou, ARKAMYS
Pierre-Yves DELPECH, ARKAMYS

基于Cadence Tensilica DSP 平台的SLAM产品化部署

John Lin, Xvisio Technology

Custom Advanced Node

基于Virtuoso SDR-DI流程实现先进工艺中的高可靠性IC设计

目前,很多版图工程师都是依据前端电路设计工程师给出的约束规则来完成布局布线的,这一过程中难免会存在由于疏忽或信息差而造成多次迭代以及资源浪费,甚至威胁芯片可靠性;并且这种方式还需要版图工程师根据所给的约束规则进行计算,手动设置线宽。Cadence 的Virtuoso Simulation Driven Routing(SDR)与Design Intent(DI)流程相结合可以实现通过仿真结果或电路设计时输入的Design Intent电流数据驱动版图布线并使其宽度自动满足EM要求,并且可以在绘制过程中随时进行EM,IR-drop以及寄生检查,大大提高工作效率,减少迭代次数。

本文主要讨论Virtuoso SDR-DI流程中涉及到的几种电流输入方式(Using ADE Assembler, CSV file, EAD Browser, HighCurrent Design Intent)以及电流驱动布线的全流程,并与传统布局走线流程进行分析比较。

Jiaxin Li, ZTE Sanechips
Yaping Huang, ZTE Sanechips Jie
Hu, ZTE Sanechips
Huili Zhang, Cadence

一种加速大规模模拟和射频IC后仿真的验证流程

近年来, 对模拟射频IC的功能要求越来越多, 导致片上集成的功能模块快速增加。且进入到先进工艺节点后, 单一模块的后仿真网表规模急剧增加。对后仿真速度以及debug效率提出了极高的要求。 除了使用更为先进的FULL-SPICE 仿真器(比如Cadence Spectre X等)提升仿真速度之外, 对后仿真输入文件格式的选择与优化同样是一种提升整体后仿真效率的方法。

本文主要讨论Cadence QUANTUS最新的smartView输出格式以及与ADE Assembler/Explorer联合加速后仿真验证的一种新流程, 并给出了与传统流程的对比结果.

Siyu Chen, ZTE Sanechips
Yaping Huang, ZTE Sanechips
Jie Hu, ZTE Sanechips
Yi Zeng, Cadence

Spectre FX对混合信号电路的快速仿真

2021年底,Cadence公司推出了新的快速仿真器Spectre FX,它在保持可接受精度的基础上,能成倍提升仿真速度,主要适合于大型的存储器电路和混合信号电路的前后仿真。

这篇文章首先将介绍Spectre FX的简单原理和使用方法,之后将重点说明如何使用Spectre FX对混合信号电路进行快速仿真以及对其结果的比较与分析。

Zhen Ma, Zhaoxin
Xinwen Ma, Zhaoxin
Xiaoguang Wang, Zhaoxin

Enhanced Virtuoso EM-IR Flow

Cadence Voltus-Fi customized power integrity solution with transistor level electromigration and current resistance voltage drop analysis technology (EMIR) can provide good solution for these problems. This presentation will include:Transistor-Level EMIR Analysis - Problems and Challenges;Virtuoso EM-IR Flow Enables Highest Productivity - Enhanced Virtuoso EM-IR Flow; DSPF extraction UI for EM-IR; Enhanced Virtuoso EM-IR setup UI; Support self-heating; High performance simulation; Spectre X simulator – enhanced accuracy and performance; Integrated EM-IR reports; Settings and results are loaded into Voltus-Fi, overlaid in Virtuoso Layout.

Chaolin Zhang, UniSoc
Weikang zhang, UniSoc
Rui pan, Cadence

Legato Application in ZTE Vehicle Analog IC Design

One of the most difficult challenges in Vehicle IC design is perform longer and more reliably in any condition or environment, the cost of failure can be very high and even life-threatening. The Cadence Legato Reliability Solution combines best-in-class Virtuoso and Spectre technologies to overcome design roadblocks, one of critical feature is avoiding failures in the field due to analog faults. This solution enables user to achieve ISO 26262 certification.

This paper used with ZTE’s case as case-study for fault simulation. The example case is designed on TSMC 7 nm technology.

Ming Li, ZTE Sanechips
Yaping Huang, ZTE Sanechips
Jie Hu, ZTE Sanechips
Yu Guo, Cadence

Improving GlobalFoundries Ultra-scale MRAM Layout Design Efficiency with Cadence Virtuoso CLE

Mary Ma, GlobalFoundries
Jiandong Cai, GlobalFoundries
Jie Yu, GlobalFoundries
Lianzhu Wang, GlobalFoundries

High-Efficient Simulation/Verification Flow with New Generation FastSpice-Spectre FX

在先进的存储类型电路设计中, 往往包含多种不同的电路类型。其复杂的工作模式需要精细的仿真验证, 而庞大的电路规模, 以及对时序,电压电流等参数的高精度要求则对仿真器的仿真容量, 速度和精度都提出了很大的挑战。SpectreFX是Cadence公司2021年新发布的下一代高速仿真器。它通过全新的快速仿真器引擎,  大幅简化了传统快速仿真器需要反复调节option的迭代步骤, 支持多核并行仿真, 从而对超大容量电路可以快速完成功能验证及性能仿真。 

本文将简单介绍SpectreFX的特点和使用方法, 分享在项目中我们使用SpectreFX帮助验证和优化设计的经验体会

Chong Zhang, YMTC

Cadence Liberate Advanced Aging Characterization

本文主要阐述Liberate Advanced Aging Characterization。Cadence的Liberate Advanced Aging Characterization 配合Tempus 工具,可以在考虑aging效应的基础上提供更好的PPA。它动态表征了不同的stress条件而不是之前单一的stress条件,同时针对不同的timing arc 表征了特定的aging variation值,加速时序收敛, 从而为更好的PPA提供了更细化有力的依据。

本文结合中兴微电子实际5nm 产品项目,从aging_timing的可靠性、数据完整性以及工具流程复杂性三个方面评估Liberate 生成Advanced Aging Library的可行性。

Cunbiao Song, ZTE Sanechips
Yimin Wu, Cadence
Han Chen, ZTE Sanechips
Weizhong Wu, ZTE Sanechips

几种电路迁移方法的对比研究

在电路设计中,由于工艺变更或者项目迭代,通常需要更新电路设计库中各器件的调用关系及CDF参数信息以满足新的设计要求。从最初的重新设计电路,到使用Customized SKILL Script更新设计库,再到后来Cadence提供的Design Migration Flow,以及近期Cadence推出的项目迁移工具VALE,一直以来工程师们都希望找到一种高效、便捷并且准确的电路设计库更新方法。

本文将介绍现有的几种电路迁移方法以及新的电路迁移工具VALE,并在操作难易程度、后期维护成本、准确性、功能完善性以及结果检查便捷程度等几个维度对几种不同的迁移方法进行综合比较,以便工程师基于不同的设计做出合适的选择。

Hang Sun, ZTE Sanechips

Digital Design and Signoff - 1

Using Conformal ECO for Functional ECO with Advanced Technology

随着芯片设计复杂度的增加以及激烈的芯片竞争环境,要求芯片的迭代周期越来越快,进而导致项目的周期不断被压缩,且新工艺和EDA新技术在芯片中的使用,也客观上增加了芯片的实现难度。产品需求以及PPA的刚性需求,迫使综合的优化力度接近极致,同时物理实现工具也为了满足PPA的要求,在物理实现环节也使用非常多优化手段,直接导致ECO的难度系数大大增加。

本文主要介绍Cadence公司的conforml工具在先进工艺下的ECO流程,借助conform工具强大的等价性检查和逻辑分析功能,既能快速的完成整个流程的ECO,又能保证eco修改点尽可能少,减少对物理实现的冲击,确保项目按时保质保量TO

Yongheng Zhu, ZTE Sanechips

从RTL到GDS的功耗优化全流程

Power as one part of “PPA”(Performance, Power and Area) become more and more important in large SOC chips, especially under 7nm technologies. AI chips schedule multi-cores parallelly for specific workload. This will provide large power consumption. Power optimization for each core is highest priority for an AI chip. With a typical power case or multi cases grouped together, we can do power optimization from RTL synthesis. Innovus for place and route departs to 3 main steps: place-opt, cts-opt and route-opt. Same flow is build by X-replay added after each step and using generated FSDB for next step. At last in signoff environment of Tempus, we using power case waveform for power opt. With such full power optimization flow we can achieve more than 10% power saving and with multi-bit involved, we can get 21% finally.

Donghua Gu, Enflame
Zhiyong Zeng, Enflame
Jinjin Yu, Enflame
Xuhui Huang, Enflame
Jiajun Zhu, Cadence
Xiangjun He, Cadence
Zefa Chen, Cadence

Chip-Centric IR Drop Co-Analysis for High-Performance Design with DLDO

传统的电源管理控制如power switch cells, LDO等已经无法满足高性能设计对性能功耗面积的追求,引入DLDO 实现多core的独立控制虽然更优,但为power signoff flow提出了更高的要求,即需要在设计早期就需要考虑封装影响来评估电源网络压降。

本文研究的重点如下:如何使用voltus工具实现power/IR signoff with DLDO, 以及仿真结果与silicon精度是否一致,如何在chip设计时优化封装带来的额外压降影响。通过该flow提高了设计和封装的协同优化,提高产品迭代速度。

Shu Jiang, Zhaoxin
Yi Li, Zhaoxin
Ling Xin, Zhaoxin

Comparison Between Concurrent Method and Die Model-Based Method in Interposer PGV Signoff

This presentation provides an overview of two methods for analyzing the IR drop for an interposer, and explores the time spent and the accuracy of IR drop results between (i) use of different die models and (ii) the concurrent flow. 

In conclusion, the IR drop results of distributed die model method and concurrent method are similar and have high accuracy. Lumped die model has the least accuracy. The accuracy of grouped die model is between distributed die model and lumped die model. In terms of running time, the die model based method takes much less time than the concurrent method.

Haiyang Song, Marvell
Jianzhong Wang, Marvell
Zugang Ruan, Cadence
Juan Peng, Cadence

基于Liberate+Tempus 的先进老化时序分析方案

当前,业内工程师一般采用两种方式进行芯片老化的时序分析:一是利用spice仿真获取能覆盖最差情况下的路径老化时序裕量,再将其以flatten ocv的方式添加在STA分析中。该方案的仿真效率较低,且会在全芯片中引入过悲观的OCV设置,导致时序难以收敛。二是初级的aging-aware STA方案,该类方案通过将老化时序裕量导入单元库,以此实现高效老化时序分析的目的。然而,传统方案仅能针对单一老化场景进行K库仿真,灵活性低,难以满足先进芯片中针对多样老化场景的时序分析需求。

鉴于此,Cadence开发了基于Liberate+Tempus的先进aging-aware STA 方案。在本文中,中兴微电子结合当前先进工艺项目,对基于tempus的aging-aware STA flow进行全方位的评估。

Qi Wei, ZTE Sanechips
Keqing Ouyang, ZTE Sanechips
Bin Wang, ZTE Sanechips
Chao Lu, ZTE Sanechips
Junhao Chen, ZTE Sanechips
Mingxiao Li, ZTE Sanechips

Spice Deck Generation and Simulation Flow for Silicon Fail Path Investigation

In this paper, spice deck generation and simulation flow is introduced to support one real silicon fail path debug.

First, silicon fail path is identify and reported in Tempus. Then with proper Tempus setup and necessary timing constraint update (e.g. case for pad), spice deck can be generated successfully from Tempus. After review and confirm spice netlist content, post processing (e.g. netlist edit) is done to support setup/hold spice simulation. After that, MC spice simulation is done and hold timing violation is reappeared in Virtuoso. After waveform check for internal nodes in flop, the root cause is found that there’s not enough margin for path from SVT flop to HVT flop in low voltage and low temperature.Spice deck generation and simulation flow for silicon debug is summarized finally.

Ying Xue, NXP Semiconductors
Glen Ge, NXP Semiconductors
Tao Chen, NXP Semiconductors
Alex Wang, NXP Semiconductors

A Power Switch Design and Analysis Flow to Lower Rush Current in Low-Power Design

This file describes how to reduce the rush current of a low power design, by some different config of power switch cells and turn on time setting, we get the balance of rush current and leakage and IR.

Yumin Liao, HED

Digital Design and Signoff - 2

Using Cadence Cerebrus with Genus to Push PPA

Cerebrus is a Machine Learning driven  optimization tool. It can be used for creating smart automated design flows for productivity and PPA.    In xxx design , we used Cerebrus with Genus&Innovus, automatically creating scenarios on a baseline flow and designer goals, generated serval primitives, then reproduced in signoff flow, significantly pushed the PPA, especially the dynamic power.

Pufan Chen, T-head
Huiyan Tang, T-head

High-Performance CPU Core Implementation with Cadence Full Flow and Machine Learning

Shrinking transistor sizes allow increased logic complexity in modern processors, for these large complex processors, physical implementation is a big challenge. This paper presents the implementation of Nerverse N2 core in TSMC 7nm technology. By using lots of cadence implementation critical technologies,about 5 percent performance improvement can be achieved compared to arm reference. Meanwhile, artificial intelligence (AI) and machine learning (ML) are emerging as powerful new ways to do things more efficiently, Cerebrus uses unique ML technology to drive the Cadence RTL-to-signoff implementation flow. Also, better PPA can be achieved after using cerebrus in Nerverse N2 core.

Chi Wu, Jaguar Microsystems
Chao Yang, Jaguar Microsystems

Acceleration of Floorplan Tuning with Mixed Placer Flow

As design size and complexity continues to grow in advanced technology nodes, floorplan is becoming more and more significant and critical for design convergence. For complex design, traditional manual macro placement is always effort and timing consuming. With mixed placement implementation flow, a new style of floorplan which is much different from traditional dataflow based floorplan was created. It provides designers with new view of macro placement, especially for those timing and congestion critical modules. In this paper, mixed placement flow was used as a guidance for floorplan tuning and help designers reduce the iteration times of a complex design.

Rong Zhang, NVIDIA
Huiping Yang, NVIDIA
Jianan Shi, NVIDIA

22FDX Low Dynamic Power Solution for Edge AI Computing Application

A case study shows that an implementation using GF 22FDX 7.5t BCCUSTOM logic library under 0.4V adaptive body bias mode, could achieve more than 40% and 20% total power saving under TT25C compared with 7.5t Ultra Low Power logic library under 0.5V zero body-bias mode and adaptive body-bias mode, respectively.

Bingxin Zhang, GlobalFoundries
Fengfeng Wu, GlobalFoundries
Tiepeng Cheng, GlobalFoundries
Hongqing Zhang, GlobalFoundries

Clock Tree Optimization Flow For Chip-Top MCU with Complex Clock Structure

For complex clock structure in MCU, clock tree design and debug are always time consuming. While at same time, clock tree quality is critical to physical design. Short clock latency helps reduce OCV and signoff timing with less cost. Proper clock skew and transition are necessary to satisfy setup and hold timing. And more, optimized clock tree design improves clock tree efficiency and save clock power.Innovus provides different ways to support building high quality clock tree efficiently. 

In this paper, clock tree design and optimization methodology are introduced for one 40nm MCU to build efficient chip-top clock tree in short time.

Glen Ge, NXP Semiconductors
Wenjing Zhao, NXP Semiconductors
Ting Gao, NXP Semiconductors
Hao Ji, NXP Semiconductors

基于HITOC DK与3D-IC Integrity的3DIC芯片物理设计

本文使用了Cadence 3DIC Integrity工具,并结合芯盟特有的HITOC(Heterogeneous Integration Technology On Chip)Design Kit,进行了3DIC逻辑堆叠逻辑类型芯片的物理设计。项目中对于Cadence 3DIC integrity 工具中的Proto Seeds(即最小分布单元)进行了拆分、分布、定义等方面的研究优化;并且对于电源网络与Hybrid Bonding间的布线排列进行了算法优化,在不影响电源网络强壮性的情况下尽可能多的获得Hybrid Bonding数量,从而增加了top die与bottom die间的端口数。

结果表明,在与传统2D芯片后端实现的PPA对比中,本实验获得了频率提升12%、面积减少11%、功耗减少5%的收益。

Rui Xu, ICLeague
Yiyuan Wang, ICLeague

Deep Partition for PPA Optimization Based on Integrity 3D-IC

摩尔定律逐渐走向终结,冯诺依曼计算架构的缺陷也在不断凸显,3D IC技术作为一种新的系统集成方式成为未来高性能芯片的必然选择。如何对2D设计进行module partition实现3D芯片堆叠是一个关键问题。Integrity_3dic平台可以通过早期的层次化partition与布局综合(EFS)的方法实现2D设计到3D设计的重整化,能够很好的优化die间互联数目、互连线长度,signal bump的排布,实现PPA优化的目的。另外,结合早期电源网络分析与早期的热分析流程评估partition的质量,SoC与后端封测团队在芯片的早期规划阶段就协同进行系统级分析与优化工作,对于减少项目迭代周期与风险也很有帮助。

Haonan Li, ZTE Sanechips
Hao Chen, ZTE Sanechips
Chenfei Wu, ZTE Sanechips
Guohua Zhou, ZTE Sanechips
Keqing Ouyang, ZTE Sanechips
Lixin Xu, Cadence
Guozhi Xu, Cadence
Yutong Li, Cadence

IP Functional Sign-Off

保序模块的formal fpv验证

保序模块时序逻辑复杂,如何处理时序关系,保证验证的完备性是保序模块验证的关键。本文介绍了将形式验证用于保序模块验证的案例,并对形式验证结果进行评估,进一步印证了形式验证在处理时序逻辑关系验证时的有效性。

Yu Zhi, ZTE Sanechips
Yaxue Zhao, ZTE Sanechips
Qifeng Liang, ZTE Sanechips
Yijun Shi, ZTE Sanechips

Shift Left Case-Study of Formal Verification using Assertion-based VIP for MHDMA Block

In this paper, a case-study of AHB ABVIP applied to MHDMA block is presented. 75.16% code coverage is reached, and 6 bugs are captured by formal platform a month earlier than the simulation-based testbench. A shift-left verification is achieved.

Shawn Zhang, Analog Devices
Mulye Ameya, Analog Devices

基于indago进行debug仿真的实践

芯片的功能和设计日益变得复杂,验证的难度也随之增加,高效的验证才能保证复杂芯片的高质量。本文基于cadence的debug工具indago ,介绍日常工作中使用indago的一些特色功能提高debug效率。本文作为使用indago方式的一种参考:

  1. indago中具有创新性的smart log功能,该功能将打印log,源代码与波形界面进行了整合处理,可以在同一界面进行log打印,代码的溯源,大大提高了debug的便利性,提高debug的效率。
  2. indigo interactive模式, 除了在依靠打印log进行debug外,利用indago单步调试的interactive 模式进一步提高debug效率。

Menghao Qian, Clounix

PZ1 IP验证仿真的加速

摘要-多媒体领域IP仿真大图、大码流所耗费时间一直是EDA仿真验证的痛点。并且随着IP更新优化、规模加大,迭代时间严重影响着项目进度、人力分配。本文将介绍利用Palladium Z1(PZ1)加速仿真提高EDA验证迭代效率。PZ1每小时编译高达1.4亿门,我们已将PZ1实践在两个多媒体领域IP的验证环境上,取得了150-300倍加速效果。

Shuo Zhang, UniSoc
Xufeng Zhang, UniSoc
Jiwen Kang, UniSoc

Block-Level Hybrid Platform

在Block级的设计开发过程中,需要在baremetal、OS两个维度进行软件的开发和调试,需要一个可以快速集成设计的Emulation平台。传统的纯RTL的SoC EMU环境需要等待RTL稳定、并经过较长的bring up时间才能启动OS,这通常在芯片投片前一个很短的时间窗口。因此并不能充分释设计在OS层级的潜在设计风险。同时这种平台的实际运行速度较慢,仅启动OS即花费相当长的时间。

Helium/Hybrid解决方案对口上述需求,我们基于CDNS Helium+Palladium Z1开发了一种Block级的Emualtion平台,可以为软件开发人员提供baremetal和OS两种使用模式。该平台比传统的纯RTL环境速度要快一个数量级,轻量且较为容易上手,节省Emulation资源,已经证实了是一个非常有价值的解决方案。

Xinling Zheng, ByteDance
Di Zhang, ByteDance

基于vManager的大规模IC验证自动化管理解决方案

vManager作为验证管理工具,高效的实现了验证回归统一化及透明化管理,验证进度及状态实时跟踪。

本方案为vManager在国内比较领先的应用,为数字化研发流程下如何实施IC验证提供了参考,为业内自动化透明及统一化管理IC验证提供了思路,为实现验证全流程闭环验证,实时知晓数据化的验证进展情况,度量验证质量提供了多维度的数据支撑。

Chaoyi Peng, T-head

PCB Design and IC Packaging

2.5D Packaging Interposer Design Based on Cadence 3D-IC Platform

The main difference between the 2.5D advanced packaging and the traditional 2D packaging is that there is an extra layer of silicon interposer, which uses the thin metal line width and fine metal spacing capabilities of the silicon process to achieve high density interconnection. This article described a design flow implemented with Cadence 3D-IC tools by which a 2.5D packaging interposer design is developed on Globalfoundries 65nm technology process. HBM2e 3.2Gbps high speed interconnect on a 3-Metal-Interposer is achieved and verified by SIPI (Signal Integrity and Power Integrity) simulation and analysis making this product has both performance and cost advantages.

Cheng Zhang, GlobalFoundries
Qing Li, GlobalFoundries
Jia Zhao, GlobalFoundries

A Scalable Solution for a Multi-Function Boards Electronic System

Products with multi-function PCBs have become the universal requirement in system design. Different functions are always designed as different PCB modules because of restricted application area. Unclear system architecture always confuse designer and result in assembly or application issue. A system-level product design solution which combine multi-board with multi-module in a system structure can perfectly solve this issue. Another advantage is  to reusing the module in different products which can avoid the waste of cost and resources for duplicate work. 

This topic is to introduce a scalable solution for system level design and implementation for multi-function PCB systems in Cadence.

Min Wei, Teradyne
Erjian Bao, Teradyne
Huixiao Xiao, Teradyne

Allegro EDM Solution Simplifies Library Management and Improves Design Productivity

SE deployed Cadence EDM (previous ADW) since 2018, we do see the benefit from EDM solution including:

  • Library management
  • Data Management and Workflows
  • Move to Cloud

 The EDM-PLM solution investigation is on-going and we are working with Cadence to take the benefit of PFM function.

Bingying Wang, Schneider Electric
Yu Chen, Schneider Electric

Celsius在封装产品热仿真中的应用

集成电路封装的双热阻模型可用于电子产品系统级散热分析,然而基于实验测试来获取双热阻需花费大量经费与时间,因此可借助仿真技术获取双热阻参数。本文针对视频监控芯片产品,包括QFN与BGA封装,利用FEM与CFD相结合的分析方法对封装产品进行建模仿真,获得温度分布云图以及双热阻参数,并将热仿真结果与实测进行比对,同时在相同输入条件下与第三方仿真工具进行对比,充分验证仿真精度,使得精确评估封装的热特性成为可能。

Ronghua Yan, Fullhan

Overcoming Signal Integrity Challenges to Improve LPDDR5 DRAM Design Quality

Designning channels for LPDDR5 memory architecture is a challenging task due to single ended interface reaching data rate of 6.4Gbps or even higher. We will introduce LP5 interface design firstly, then will compare cascaded S-paremeter with merged 3DEM modeling, at last optimize channel SI performance based on comparison result.

Frank Ma, CXMT
Lisa Wei, CXMT
Zuli Qin, Cadence

112G高速数据链路通道设计和信号完整性仿真

5G full-optical bearer network high-speed data link design technology is complex and challenging. This paper discusses many technical challenges faced by 112G SerDes link. Based on the Sigrity simulation tool, the link is verified and optimized. This helps the rapid launch of full-optical network communication equipment and improving product competitiveness.

Jian Huang, ZTE
Zhiwei Yang, ZTE
Daishan Zhu, ZTE

IR Correlation Between Post-Silicon Measurement and Voltus-Sigrity 3D-IC Co-Simulation

Using X-replay to do a simulation with SDF, we will get netlist FSDB with delay info to count glitch power together. It will help us to get the real toggle for simulation just like it works on real silicon. Finally, we use Voltus 3DIC platform co-simulation with a pin-based package model generated by Sigrity. The full-system IR simulation show 121mV droop just at the same capture cycle as we measured by ATE. It is a good correlation for cadence 3DIC tools with a silicon proven.

Jinjin Yu, Enflame
Rui guo, Enflame
Xurong Cao, Enflame
Donghua Gu, Enflame
Haitao Qian, Enflame
Zheng qin, Enflame
Yaoyu Liu, Enflame
Zugang Ruan, Cadence
Zefa Chen, Cadence

SoC Verification and System Solution

Benefits of a Common Methodology For Emulation and Prototyping

Michael Young, Cadence

PSS with Perspec System Verifier Used in Qualcomm SDC SoC DV Team Advanced

The legacy SOC tests manually development flow has various challenges.With the usage of Perspec, most of the challenges can be resolved. This year, the advanced Topics is:

  1. Compare the source code of previous SOC tests manually develop flow with current PSS enabled automation flow. With comparation, we can see how do we resolve problems like the test case randomization, multi-threading, automatic generation of tests and re-useable across chip, etc.
  2. How to resolve C to SV communication Flow with PSS enable environment.
  3. How to generate performance testing.

Shengyi Zhang, Qualcomm
Zhengsuan Wang, Cadence

基于Cadence CHIACE-LITE和自研BFM的多核SoC系统数据一致性验证

Using CHI&SVD-VIPs to accelerate cache coherence verification and performance optimization helps us efficiently and quickly verify the correctness of the architecture design and system integration, which greatly shortens the chip design time and saves the cost.

Xiongzhi Wang, ZTE Sanechips
Yan Chen, ZTE Sanechips
Weisong Zhang, ZTE Sanechips

Accelerated Verification of GPU DP Display on the Z2 Platform

Over the past decade, graphics processing unit (GPU) technology has developed at an astonishing rate, making huge strides. GPU is the computing power engine of the future and the Holy Grail of the chip industry. In the research and development process of GPU chips, graphics display is an indispensable part. As the scale of GPU chips continues to increase, traditional simulation verification has some limitations in terms of graphics simulation verification speed and verification scale. Moore Thread has built a set of accelerated GPU DP graphics display verification process based on the Pallaium Z2 platform, which strongly supports the chip's tape-out and early software development.

Chongyang Wang, MOORE THREADS

ASIC Power Analysis Full-Cover Flow Base on Palladium DPA2.0 and Xcelium PowerPlayback

由于目前芯片设计的复杂度集成度逐步的增加,在芯片流片前拿到更新准确的Power 数据显得尤为重要,IR Drop和Supply的分析数据都是有效降低芯片流片风险的重要数据支撑,SDF replayer一款Power 分析工具,能够在项目TO之前,通过RTL前仿波形、PR_Netlist、SDF等后仿输入模拟后仿行为,提前拿到相对准确的Power相关Case的后仿波形;进而输出给IR Drop的分析及Power Supply的分析和估计。

我们和相对成熟的Synopsys的PAA做了实验和对比,并给出应用实例。

Yanan Luo, UniSoc
Tao Liu, UniSoc
Yuxing Zhang, UniSoc

System Analysis

Multiphysics Simulation Innovation

Jian Liu, Cadence

112G Cowos + Package Signal Integrity Co-Simulation

This document introduces a new signal integrity analysis method designed by 2.5D 112G CoWos. The solution provided in this document is based on the TSMC 2.5D CoWos design. Using the Clarity3D software  from Cadence®, it constructs a combination model of cowos+package, and analyzes the 112G multi-channel frequency domain. In addition, it solves the C4bump repetition and impedance discontinuity problems, that are caused by the modeling of  CoWos  and package. Furthermore, it avoids the inconsistency between the simulation analysis circuit and the actual physical circuit, and helps to accurately verify the performance of 2.5D CoWos and package.

Shuai Xue, ZTE Sanechips
Liyang Xu, ZTE Sanechips
Feng Wu, ZTE Sanechips
Bin Yu, ZTE Sanechips
Tuobei Sun, ZTE Sanechips
Keqing Ouyang, ZTE Sanechips
State Key Laboratory of Mobile Network and Mobile Multimedia Technology
Haidong Zhang, Cadence

A Disruptive CFD Technology Applied to Automotive Simulations

Olivier Thiry, Cadence

基于电源CPM模型的全链路仿真及测试校准流程

This article embarks from the board and pkg to die, and we use sigrity software to do the PDN simulation optimization for the whole channel, and finally we will import CPM model to do the power supply noise simulation, and also to do the calibration of simulation results and the power supply noise measurement , this software will fully prove that the simulation precision of this software, and make accurate assessment before the cast slab high current power supply noise is possible!

Gang Huang, EDADOC

2.5D Interposer HBM2E Design SI/PI Simulation and Co-Analysis

本文主要内容是分享一个hbm2e仿真案例和SIPI联合仿真流程:首先对interposer的布线方案进行仿真确定;然后通过topxp的system SI仿真验证所选方案的眼图结果,可以比对优化前后的差异,进一步确定最优方案;下一步通过topxp的system PI仿真得到某些特定激励下interposer上的电源噪声;最后在topxp中做system SIPI联合仿真。在仿真hbm2e的时候,信号使用在系统级PI仿真时相同的激励模式,同时把PI仿真的电源噪声结果作为激励注入interposer的power上。

Zheng Qin, Enflame
Xiangfei Yang, Enflame
Kai Wu, Enflame
Xuesong Qiu, Enflame
Haisan Wang, Cadence
Baibing Xu, Cadence

GDDR6系统串扰优化

对于高速并行接口GDDR6,由于信号工作在很高的data rate,不论信号的时序和电平裕量都变得很紧张,所以串扰的影响会成为制约系统性能的瓶颈。本文将结合封装和PCB来两个方面来介绍串扰控制的要点。

Guohua Wang, KUNLUNXIN

LPDDR5 CA拓扑分析

针对ca信号在一拖四的情况下,不同拓扑的信号质量分析,并结合工艺可实现行,推荐最优解决方案。

Ying Zhang, ByteDance

Clarity Application in Signal VSWR Optimization

在高速互联时代,随着系统功能的复杂度以及速率的提升,芯片封装的ball map设计不再仅是布线排列,设计过程中需要提前考虑信号之间的相互影响以及信号本身的质量。在封装布线完成后再做仿真的方法已经不能够满足需求, 会拉长设计周期, 所以一个pre-layout的研究工具尤其重要。本文基于Cadence设计的PKG pre-layout工具(PKG_Via_Pattern tool),以QLINK以及RF信号为例,对芯片封装的Ball map布局进行仿真,再加入PCB pre-layout做链路仿真,评估风险等级,缩短封装ball map设计周期。

Linping Chen, Qualcomm