CadenceLIVE Silicon Valley – OnDemand
Enabling Next-Generation Automotive Systems
The level of vehicle automation is the key driver for new E/E architectures, sensor architectures and high-bandwidth in-vehicle communication. Radar, Lidar and Camera are the key sensors as part of the new zonal architectures to enable autonomous driving.
Hence these new technologies will dramatically increase the electronic content of a car which require to integrate more functionality on a chip, rather than on a PCB to provide the performance, safety and reliability in a small form factor device. A new class of high-performance System-on-Chip (SoC) and/or System-in-Package (SiP) is needed to process all sensor data and fuse them together.
As a result autonomous driving platforms targeting maximum performance, running at giga-hertz frequencies need to be designed and optimized for scalability, power efficiency, thermal and EMI robustness.
This talk provides an overview on automotive trends and the implications for SoC and system design for sensors and automated driving platforms.
Robert Schweiger, Design Verification Engineer, Cadence
Development of Radar Algorithm for the Tensilica Processor
Autonomous driving needs different sensors to detect person and objects in the near and far field. Radar based sensors are a good candidate because of robustness against different environmental effects like rain. Radar sensors with different transmit and receive antennas allows beamforming. With beamforming and follow up data processing range, angle and distance of persons or objects in relation to the radar sensor can be calculated. Range and velocity can be calculated by FFTs but for the angle an different algorithm is necessary. Often the music or and adoption of the music algorithm is used to calculate the angle. The FFT can be calculated with mid effort but the music algorithm needs a huge computation power. An efficient implementation for an Tensilica B20 is shown in the presentation and ideas to speed up the algorithm by usage of TIE extensions is also presented.
Andy Heinig, Fraunhofer Institute Dresden
FMEDA-Driven Analog/Mixed-Signal and Digital Safety Design
The next generation zonal architectures will build the foundation for truly autonomous driving. This revolutionary E/E architecture will rely on highly integrated System-on-chips (SoCs) that are connected via high-bandwidth in-vehicle networks. By integrating multiple functions into a high-performance SoCs it will also enable OEMs to significantly consolidate Electronic Control Units and safe cost.
However, to ensure that these complex SoCs meet rigorous safety standards while accelerating the ISO 26262 certification process a highly automated and integrated functional safety solution is needed.
In this talk a new FMEDA-driven safety methodology will be introduced that enables safety design,
analysis and verification for analog, digital and mixed-signal SoCs.
Robert Schweiger, Cadence
Qualifying Modus Fault Coverages for Automotive Designs Using the Xcelium Fault Simulator
The ISO26262 standard provides guidelines for hardware and software to ensure functional safety of an automotive system. To ensure that the overall system is robust, it is critical to ensure that the errors in software tools used for functional safety compliance do not lead to safety goal violations in the field. To build confidence in a software tool, ISO26262 mandates qualification of a software tool to minimize the risk of systematic faults and to ensure that the development process is robust.
Design for test (DFT) plays a key role in addressing how IP suppliers and integrators from companies across the supply chain can work together to meet safety goals while meeting the quality required of shipped devices. Automated test pattern generation (ATPG) tools leverage DFT structures to generate test patterns that help achieve high-coverage targets required during manufacturing tests and in-field system tests. In this work, we present a novel method to qualify the Cadence Modus ATPG tool for functional safety using the new Cadence Xcelium Fault Simulation (XFS) capability that ensures fault coverage metrics are reported correctly and free from software errors. This is achieved by using XFS to independently fault grade ATPG tests generated by the Modus tool in simulation. This is one of the first documented use of XFS for Modus tool qualification that meets the tool qualification requirements per ISO 26262 - 8:2018 Section 11.4.6.
Benjamin Niewenhuis, Texas Instruments
Devanathan Varadarajan, Texas Instruments
Parvathy Sasikumar, Texas Instruments
Automotive Functional Safety Mechanism Designed in GlobalFoundries 22FDX Platform
The presentation introduces GlobalFoundries 22FDX as the technology and design platform of choice for the next generation of automotive designs. Automotive design imposes stringent requirements for reliability and Functional Safety (FuSa).
Reliability is subsumed under AEC-Q100 requirements known as Automotive Grades. 22FDX is qualified for Automotive Grade 2 and 1 application profiles.
Functional Safety summarizes all measures to ensure that safety critical functionality is not failing and subsequently causing hazards for users of automotive silicon products. ISO26262 standardizes various aspects of describing functional safety requirements, mechanisms to ensure and methodologies to analyze functional safety. Functional Safety is not only essential for automotive designs but also important for other safety critical electronic systems such as Aerospace, Medical, or Industrial Automation.
This presentation briefly summarizes the features of the 22FDX AG1 Automotive Design Platform. The presentation focuses on how the digital design platform supports functional safety measures.
This presentation describes Cadence Genus and Innovus toolset based “safety-aware digital design flow” to introduce FuSa features on a safety critical design, designed with GF 22FDX based on Automotive Grade 1 (AG-1) 9-track std-cell library. The FuSa features covered in the presentation are “TMR (triple mode redundancy), DCLS (dual core lock step) and high RVI (redundant via insertion) to fulfill DFM AG1 requirements”. It also gives an overview of the current Cadence based FuSa design flow status as well as the open topics we had to deal with.
Finally, physical design results are summarized, with key focus on the impact assessment of FuSa feature introduction on the PPA results around a Tensilica B10 core design.
Nidhish Gaur, Globalfoundries
Falk Tischer, Globalfoundries
5x Faster Library Characterization in Cloud
Library characterization for an advanced node design is a compute-intensive task -- ideal for a scalable and flexible cloud. In this presentation M31 will describe a Library characterization methodology that enabled 5x faster delivery using Liberate on Cadence-managed CloudBurst.
Philippe Hurat, M31
Pegasus TrueCloud for Giga-Scale Physical Verification Using Hybrid Cloud on Amazon Web Services
Historically, physical verification jobs have been very compute- and memory-intensive. Silicon designers are often resource-challenged to run physical verification on designs that can consume 1000s of CPU cores and require multiple days to complete. The new Pegasus TrueCloud enables designers to run physical verification jobs from on-prem compute resources onto the cloud and has a massively scalable architecture that can reduce design cycle time.
Ahmed Elzeftawi, AWS
Dibyendu Goswam, Cadence
Best Practices for Running Cadence Spectre X on Microsoft Azure Cloud
Circuit simulation is one of the key workloads for both AMS and logic design. Configuring and matching infrastructure in the cloud is key to customers getting the best performance and value with this workload. We will discuss best practices on setup and resource selection of Azure resources to run Spectre X on the cloud.
Richard Paw, Microsoft Azure
Computational Fluid Dynamics
Realizing CFD Vision 2030
Jeffrey Slotnick, Boeing
Output-Based Mesh Adaptation for Low and High Speed Aerospace Regimes
Output-based mesh adaptation is achieved by coupling the MIT SANS finite-element solver and metric optimization with the Pointwise mesh generator. The interface between SANS and Pointwise is a fine-grain point cloud of sizing requests that drives the Pointwise meshing algorithm. Viscous adaptation is achieved via a hybrid approach where sizing requests drive isotropic refinement and viscous layers are apriori generated. Adaptation results are shown for 2D inviscid and viscous airfoil cases starting from extremely coarse initial mesh resolution, as well as select 2D hypersonic test cases.
Dr. Marshall Galbraith, MIT
A Disruptive CFD Technology Applied to Automotive Simulations
Cadence presents a new technology based on advanced numerical algorithms that yield high scale-resolving accuracy on low-cell-count grids within fast turnaround times. The solver is fully integrated into an end-to-end platform that streamlines the geometry preparation, mesh generation, simulation, and co-/post-processing, leveraging the power of GPU infrastructures with minimal user intervention
Olivier Thiry, Cadence
Towards Wall-Resolved Large Eddy Simulation of the NASA CRM High-Lift Configuration: Preliminary Results
Supported by DOE's INCITE program, we are performing a wall-resolved large eddy simulation (WRLES) of the NASA Common Research Model (CRM) high-Lift Configuration on Summit. Progresses in many areas are needed to enable this undertaking: adaptive high-order methods, high-order mesh generation, implicit solution algorithms, and efficient implementation on extreme scale CPU/GPU clusters. Preliminary results will be presented.
ZJ Wang, University of Kansas
Nick Wyman, Cadence Design Systems
Kristen Karman-Shoemake, Cadence Design Systems
Advanced Modeling of Hypersonic Reentry
Maximilian Maigler, UniBw Munich
Custom IC Design and Simulation
Lessons Learned from OP Point Back-Annotation Enablement in PDKs & Fully Automated Testing
Vivienne Miller, GlobalFoundries
Stephen Burgess, GlobalFoundries
Illia Petrovitch Reznichenko, GlobalFoundries
Romain Feuillette, GlobalFoundries
Utilizing Advanced Node snapPatterns for Mature Node Layout Placement
Eduard Raines, Analog Devices
Brock Moore, Cadence
Optimized Methodology for HV DRC Flow
In the ever-shrinking world of chip design, designers are on the lookout for fitting more geometries in a limited space. Design Rule Checks (DRC) enforce that net shapes maintain minimum spacing. The minimum spacing is also dependent on the difference in voltage values of these net shapes. Conventional methodology, of difference in voltage calculation on net shapes and subsequent spacing checks, leads to pessimistic results. For various functionally correlated nets in the design, it is possible to relax the minimum spacing requirement thereby making the layout compact in terms of space utilization. The paper describes a method to reduce pessimism in voltage-dependent DRC for functionally correlated nets. The described method covers an end-to-end solution, where dynamic voltage specs are derived from simulation results then implemented in the layout, and subsequently gets validated before running the signoff DRC check. The method also includes debuggability of the violations reported by the signoff DRC run, which considerably improves the usability of the solution for end-users.
Byron Caloz, Intel
Wee Lian Lim, Intel
Nur Syarafina Zahari, Intel
Sevanthy Gandhi, Intel
Boon Hoe Teh, Intel
Boon Chin Teoh, Intel
Faster Signoff of FPGA Layouts by Divide and Conquer Method Using Virtuoso CLE
Advanced node challenges contributed significantly in time and iterations to complete design cycle especially for complex custom mixed signal designs for the IPs which go into reconfigurable computing systems like FPGA chips and common standard methodologies are not able to address new design challenges, improve time to market and enhance the quality of products.
Based on the layout planning and design complexity, multiple designers work in parallel in order to meet the critical projects requirement and deadlines. In existing layout flow, design manager who is handling top level layout will do the layout partition and decide the free area for other layout designers working on same project , other designer would proceed on different cell view and complete task in allocated area within locally created library and later share his library path to design manager. Since in existing flow multiple designers cannot work together and edit on single layout cell view, therefore it is very time consuming for design manager to complete all task of planning, assigning works, integration and repeat the same task at various stages of layout developments.
Physical signoff is very challenging during the tape out week of the development cycle. At this stage, in existing layout methodology, there is no way where layout can be selectively partitioned and assigned to multiple designers in order to reduce the overall task and to fix massive number of DRC errors.
Above problem areas and design complexities are drastically reduced by novel way of utilizing the Advanced Virtuoso Concurrent Layout Editor (CLE) in layout development.
Virtuoso CLE provides an editing environment that lets several designers to work concurrently on the same design at the same time, helping in cutting long design cycles and improving productivity. In this paper, two use cases are discussed where we leveraged area and layer-based CLE methodologies and its benefits during routing and expediting DRC sign-off.
CLE is majorly used for fixing the DRC for a bigger block with partitions based on area/layers. Along with DRC fixes we can make use of CLE in routing phase also if the design meets some specific requirements. Here in AMD we identified such designs to leverage the advantage of CLE and complete the routing in shorter time without compromising on quality of the design. Design requirements are explained in this paper with example which are implemented with CLE and reduced the time to market.
An IO block, which is compatible with CLE, designed with conventional way of routing, would take at least 8 working days for 1 resource. When we use CLE with 3 resources, all the routing and integration was completed within 3 working days. This resulted in reducing the overall design time.
After routing phase and LVS clean, CLE has an advantage in taking DRC fixes as well. With the advantage of Area/Layer based partitions one can fix the DRC based on requirements. With given observation area-based partitions are much helpful while fixing the base/frontend DRC, as it may need some device/block movements and drawing the flat layers. When it comes to backend DRC fixes layer-based partition gives full-advantage in reducing the design cycle.
Before running the DRC or any Physical Verification (PV) checks for partition level edits, one should aware of the virtual memory (VM) concept and how CLE uses VM to improve the disk space utilization and makes faster in opening the design. CLE saves only incremental edits in the partition view (disk space) to make it light weighted and the master view will be loaded into VM dynamically when the cell is opened. User will see both combined in the single layout window. As partition view has incremental edits only, PV tools try to run the checks only for these few incremental edits rather than complete design, so we might get incorrect reports due to this. To avoid this issue, one need to export GDSII/OASIS with Virtual Memory Export (VME) option enabled, Cadence is providing this option on CLE canvas. The exported GDSII/OASIS need to give as an input to the PV tool. As this is multistep process and error prone. A customized inhouse PV GUI has been developed which is capable of exporting GDSII/OASIS and run selected PV check with a simple button click and helps user to make it fast with more accuracy.
Another IO block for backend DRC fixes with initial estimate of 5 working days for 1 resource and with CLE layer based partition with 3 resources could complete all the DRC fixes within 2 working days only without compromising on the quality of the layout at any given point of time.
CLE helped us in reducing the design cycle by a great extent in both routing and DRC fixing phase of the design in all possible blocks, which eventually helped in achieving the tape-out deadlines hassle free. Here are the results tabulated with and without CLE for set of blocks which are worked on.
1. Inter-block level routing time reduced from 8 working days (1 resource) to3 working days (3 resources)
2. Backend DRC fixes for a top-level block signoff time reduced from 5 working days (1 resource) to 3 working days (2 resources)
Deepak Agarwal, AMD
Apparao Yadalapurapu, AMD
Naga Rajender Vijapur, AMD
Gautam Kumar, Cadence Design Systems
Yuan-kai Pei, Cadence
Vishesh Kumar, Cadence
From Spec to Virtuoso
Systems Engineers cover the requirements and operating conditions of analog-mixed signal circuits in a structured way at an early stage. During the development if the IC changes can happen to those requirements and operating conditions for example due to changed customer requirements.
While in current flows the designers carry over the information from the spec to the design environment often in an unstructured way, Cadence’s Verifier together with the Setup Library Assistant offers the possibility to bring this information from the device specification to the simulation in a structured way. Through the given API functions the specification data can be pulled into the Virtuoso environment without manual interaction. In addition, a frequent sync between spec and design environment ensures that no changes are missed and the environment ensures that simulations meet the requirements under all defined operating conditions given in the device specification. Designers do not have to go and change the individual Maestro states, but changes can be applied automatically without manual effort.
Jerry Chang, Texas Instruments
Juan Verdu, TI
Angelika Keppeler, TI
Simplified Functional Verification Using Legato Reliability
Tahsin Alim, Renesas
Fast and Accurate FastSPICE-Based Verification of Analog and Mixed-Signal IPs
Design and verification of mixed-signal IP is becoming increasingly challenging with advanced-process nodes. Increasingly stringent design specifications to meet end customer demands are leading to higher design complexity. Verifying these complex designs is complicated because of evolving newer architectures, higher clock speeds , increasing design sizes due to advanced-node processes, and the exponential increase in layout parasitics. The need to accomplish verification closure in tight schedule is driving the need for faster circuit simulators which simultaneously meet the required accuracy for these designs. To meet this need, Samsung Foundry and Cadence have been keeping in tight collaboration, and as a part of such co-workings, Samsung Foundry has evaluated the Cadence's new FatsSPICE simulator, Spectre FX Simulator, on Samsung Foundry advanced node. This presentation focuses on how Cadence’s Spectre FX FastSPICE simulator was used to verify Samsung Foundry’s AMS IP with fast performance and the required accuracy. We will demonstrate how the simulator was set up and used to verify PLL, SRAM, and PCIe designs on Samsung’s latest process nodes.
Jay Madiraju, Samsung Foundry
Sudhir Koul, Samsung
SKILL Coding Enhanced by Machine Learning
Vivienne Miller, GlobalFoundries
Nolan Pavek, GlobalFoundries
Romain Feuillette, GlobalFoundries
Useful Utilities and Helpful Hacks: Part II
SKILL customizations and development leveraged the Navigator, Annotation Browser and VDR flow. The development was driven by design ECO’s which create the need to find, debug and manipulate layout design objects.
Impactful utilities include understanding the Cell Instance hierarchy and all dependencies which is essential for large designs with multiple levels of hierarchy. At the net level a utility to show net intersections, device connections and hierarchy with results displayed in the Annotation Browser is a significant aide in debugging and comprehension. For a design impacted by voltage dependent finding the nets with voltage properties or instances is made easier with a utility which groups the results in the Navigator and in a summary. If there truly is a bug, a comprehensive one click solution which packages data utility to recreate all aspects is captured. Finally, before a design is streamed out, a thoroughly set of check and fix scripts are available. The initial motivation and hints and hacks on how to implement are also included.
David Clark, Intel
Julia Perez, Cadence
Using Spectre X Simulator in 7nm Mixed-Signal Design Transistor Level Verification
Mixed-signal design and verification become increasingly challenging at 7nm and below, especially for digital and analog co-simulations. Usually, mixed signal co-simulation is required to run at higher level with large scope of analog and digital circuitries. However, the traditional flow cannot achieve the fine accuracy required by high frequency components in analog circuits. As a result, the simulator step time would be significantly reduced, and the simulation time increases tremendously, up to 1 month. Hence it is critical to improve simulation throughput and reduce resource consumption for such cases.
To address this challenge, we developed a new simulation flow using Spectre X. In this flow a single simulation environment and a single simulator are used for both analog and digital circuits. Digital RTL blocks are imported into Cadence Virtuoso schematic and connected to analog blocks. The Spectre X simulator is utilized to perform functional verifications at the transistor level. Fine time steps required by high frequency components such as VCO are accommodated in simulations. Simulation times are reduced from months to less than one week. Block level simulation and top-level functional verification can be performed in the same environment, eliminating the need of switching design flows.
In this paper, we will demonstrate the efficiency of the flow using a PLL top-level verification test bench that includes the entire analog PLL blocks and digital circuit during calibration. The VCO is composed of passive LC components with RF models. The simulation time is in the range of ~10us, and the verification is completed within one week. This flow is proven efficient for functional verification to detect potential bugs at early design phase. It reduces the design cycle and provides confidence for final design sign-off. Challenge of digital circuit debugging will also be discussed.
Pei Yao, AMD
Lei Zhou, AMD
Stanley Chen, AMD
Moustafa Mohamed, Cadence
Understanding On-Die Thermal Mismatch with Electrothermal Simulation
TI is collaborating with Cadence on the new electro-thermal DC and transient analysis in Spectre. We start by explaining the new electro-thermal transient and DC analyses in Spectre, highlighting its potential and details of our collaboration with Cadence to improve Spectre Thermal to production quality. We address the intricacies and limitations of technology and package abstractions, before we go describe memory and CPU requirements.
We conclude with describing our results from the electrothermal simulation of a precision amplifier, where we were able to predict
CMRR and PSRR performance.
Stephan Endrass, Texas Instruments
Sudarshan Udayashankar, Texas Instruments
Mayank Jain, Texas Instruments
A Versatile Characterization Flow for Analog IP
Characterization of analog-mixed signal macros have been challenging at Intel. Liberate-AMS has been adopted for timing, pincap characterization of analog IP (AIP) due to ease-of-setup, fast run time, and SPICE like accuracy. It’s hybrid partitioning technology for timing and pincap helps in characterizing mixed-signal blocks efficiently and accurately. We open this CDN Live presentation discussing the “hybrid flow” and how it enabled balancing characterization runs between accuracy for most critical paths and agility of optimal runtime for large designs. We briefly introduce noise modeling flow together with accuracy correlation and runtime data for timing, pincap, and LVF. The tool’s versatility is availed through the flow developed by integrating it with Virtuoso ADE flexibly which provides for a greater ease of use through smake flow. The smake flow streams line the characterization data management and greatly improves the characterization flow usage within design environment. It provides designers the flexibility to quickly shift from the GUI-based to command-line-based environment to produce libraries from pre-existing setups. Finally, we conclude with recommended future improvements.
Sai Varun Krishna Tatipamula, Intel Corporation
Design ANALYTICS AND PREDICTABILITY IN CADENCE VIRTUOSO
Flex Logix Technologies is a semiconductor startup designing complex AI edge inference accelerator and the leading supplier of eFPGA IP using Cadence’s Tools and Cliosoft SOS Design Management Platform to handle the complexities of product development.
Flex Logix is a reconfigurable computing company providing AI Inference and eFPGA IP solutions based on software, systems, and silicon. Flex Logix InferX™ edge inferencing solutions provides flexible high-performance AI inference processing for less cost and lower power than GPU-based competitors. Flex Logix is also the leading supplier in eFPGAs, EFLX, with more designs, metal stacks and configurations supported. We have been creating award winning eFPGAs for years and EFLX eFPGAs of any size can be delivered in a few days with available processes which are in 180nm down to 6nm. Reduce power, add reconfigurability and accelerate your chips with EFLX eFPGAs.
Cliosoft SOS integration with Cadence Virtuoso provides a unique capability built right into its Library Manager. It allows project teams to track actionable values on design objects and display them like spreadsheet columns. Design teams can track actionable project metrics such as Effort Level, Percent Completed, and Completion Dates natively within the Cadence Virtuoso interface. Each custom column can be associated with a built-in function such as count, total, average, and even custom functions using Cadence Skill. This feature helps provides design team’s visibility and functionality to manage projects efficiently. It also provides Design Manager with real-time design intelligence with automatic tracking, analysis, and visualization.
Amit Varde, Flex Logix Technologies
Advancing design and verification of Mixed-Signal Systems through Cadence Virtuoso ADE - MATLAB/Simulink Integration workflows
The challenges of today's advanced silicon process nodes, as well as stringent performance targets, escalate mixed-signal design complexity. As these designs are created in different abstractions and design flows, exhaustive verification routines are needed to ensure functional and specfication compliant designs. Design automation workflows that scale and improve various stages of the IC development process including digital design, analog and mixed-signal design, pre-silicon verification, and post-silicon validation are critical for the success of these complex engineering tasks.
In this presentation, Cadence & MathWorks will present the latest advancement in verification and visualization techniques through combining the MathWorks Mixed-Signal Analyzer app and Cadence ADE workflow to enable seamless data post-processing. We will also present the Simulink and Cadence Virtuoso integration workflows such as co-simulation and Simulink model export through DPI-C code generation.
Jesson John, MathWorks
Digital Design Advancements with AI
Broadcom Evaluation of Cadence Cerebrus Machine Learning Optimization in PNR Flow
From an early pioneer in DOCSIS to today’s unquestioned industry leader, Broadcom has developed the industry’s strongest and most widely deployed solutions for both head-end equipments and CPE products. Broadcom continues to lead this space and is always looking to improve design flows to achieve best performance with reduced time to market. In this session, we will talk about how Cerebrus machine learning tool works, our evaluation results, and how we are using this flow to help improve performance of our next generation chip, while also increasing engineering productivity.
Tao Wen, Broadcom
Renesas Deploys Cerebrus for Improved PPA and Shortened Development Time in High-Performance MCU Design
As the world's leading microcontroller vendor, Renesas Electronics offers a wide selection of microcontrollers (MCUs) and microprocessors (MPUs). In order to develop these products quickly and with high quality, Renesas is always working to improve design efficiency by introducing the latest design flows, tools and by automating verification.
Recently, we adopted Cadence's Stylus digital full flow from logic synthesis to implementation and signoff, and also applied Cerebrus with machine learning optimization to both improve PPA and shorten development time, which have now been used to tapeout a high-performance MCU design. In this session, an overview of each initiative and its effects will be presented.
JJ Wang, Renesas Electronics Corporation
Norio Sugino, Renesas
Driving Productivity and PPA Gains with Cadence Cerebrus
Amit Bandlish, NVIDIA
SARC tapeout industry leading GPU using Cerebrus AI optimized flow automation
Alex Spencer, Samsung
Advance Node PPA Entitlement to PPA Boost by Adopting Cerebrus ML-Driven Approach
As MediaTek push power, performance and chip die area of the latest System on Chip (SoC) devices they need to adopt the latest foundry nodes quickly and efficiently. During a recent move to advance node, Mediatek had to perform new node’s PPA entitlement then further PPA boost by optimizing the complete implementation fullflow and block floorplans. Rather than spending many months of manual effort, MediaTek deployed Cadence Cerebrus ML optimization to automate the whole process. This leaded to achievements of competitive PPA qualities under demanding project schedule requirements. Attend this session to learn more about how MediaTek improved PPA and engineering team productivity using Cadence Cerebrus ML optimization.
Tony Han, Mediatek
Deriving Best in Class PPA for Complex Hierarchical SOC Using Cerberus Optimization System
Traditional methods of tuning synthesis and place & route recipes have become increasingly costly to optimize power, performance and area (PPA) in digital designs. The parameters that influence PPA have also increased manifold with the complexities of sub-10nm geometries and significant advancements in EDA tool capabilities in recent years. In this paper, we will discuss the significance of PPA in various phases of project execution and how ML based capabilities can be used to augment traditional workflows. We will discuss Cerberus – ML based optimization flow in detail, and finer integration aspects of the solution in Intel design system and its IT infrastructure. We will also present how Cerberus was used in a production SOC execution context to (i) improve PPA and (ii) accelerate design convergence. Additionally throw light on future roadmap on how Cerberus when enabled fully on cloud can potentially transform our future design execution and mode of work.
Raghavendra Vasappanavara, Intel
Digital Design and Signoff
Framework for new feature evaluation in RTL using Genus Synthesis Solution
New feature evaluation in RTL requires physical design feedback. Traditionally, floorplanning to enable physical design requires a lot of manual effort. Especially when it comes to complex IP or SoC, many engineers might work on different features of the same module. This presentation describes a feasibility flow utilizing Genus predict_floorplan feature to generate a floorplan for quick module level synthesis and placement. The flow enables designers to evaluate PPA of new RTL release on any selected modules, which are usually smaller than the physical partitions. Cadence flowtool based YAML flow makes the setup easy to keep pace with the implementation flow. This flow brings in scalability of RTL early evaluation and comparable PPA results with a minimum setup and maintenance effort.
Tianyu Huang, Samsung
Cory Krug, Samsung
Nimish Agashiwala, Cadence
Using Tempus’s SmartScope and DSTA to get Fastest Design Closure with best PPA.
For years, Nvidia, like most companies in semiconductors space, have made use of physical design flows that perform timing optimization in multiple stages. Initially, partition level implementations perform timing optimization within each partition. This is followed by inter-partition and inter-chiplet timing optimization to attain fullchip timing closure. Cadence Tempus has all the necessary tool features to allow development of design flows where partition, inter-partition and inter-chiplet timing optimization can occur simultaneously at each level of design hierarchy. This leads to tremendous improvement in runtime needed for timing closure. Taking advantage of Tempus’ simultaneous hierarchical timing optimization features, fullchip timing closure can be achieved as design partitions are run through the place and route flow. This eliminates the subsequent stages of timing closure, and leads to shorter time-to-tapeout. Additionally, these features also allow development of hierarchical chiplet place and route flows.
Arif Mirza, NVIDIA
Tempus™ Eco and Smartscope based Chiplet Opt
DTCO Methodology for Improving Routability in Advanced Process Node
Design-technology co-optimization(DTCO) is one of key technologies to keep scaling down chip area in advanced process nodes. One of challenging tasks in DTCO is to secure of the sufficient amount of routing resource under the shrinking the routing resource and increasing complexity of design rule condition. In this work, we propose several design methodologies to overcome the severe design constraints in advanced node such as minimizing the routing usage by using the direct pin connection method with the various pin location. Our experiment demonstrates that additional area scaling can be achieved through the industrial test-cases using the proposed methods.
Yunseok Noh, Samsung Electronics
Jooyeon Kwon, Samsung Electronics
Yongcheul Kim, Samsung Electronics
Sangdo Park, Samsung Electronics
Hyung-Ock Kim, Samsung Electronics
Sangyun Kim, Samsung Electronics
3D Partitioning and Placement for Next Generation 3D-ICs with Integrity 3D-IC
Multi-chiplet design and packaging introduces extra design and analysis requirements like system planning, TSV and Micro-bump insertion, extraction, electrothermal analysis, cross-die STA, and inter-die physical verification . A brief introduction to Cadence® Integrity™ 3D-IC platform will be presented which integrates planning, implementation and analysis to address the new requirements of 3D-IC design and signoff for different packaging styles.
In addition, partitioning a design into multiple chiplets is a significant starting step for multi-chiplet design. For full-stacked 3D designs , it is important to have an automated way to do partitioning, placement, bump assignment and optimization along with 3D structures implementation. With methodology evolving for different types of designs, a top-down and a bottom-up approach for implementation is possible. In this session, Cadence R&D will present the different approaches to 3D partitioning and implementation and upcoming features necessary for efficient stacked-die designs.
Vinay Patwardhan, Cadence
MIMCAP integration flow Using Innovus/Pegasus
At lower process nodes, device density increases. And, at high gigahertz frequency, simultaneous switching of densely packed devices can cause sharp fluctuations in voltage, current in power supply network, leading to sharp IR drops and noise. Because this phenomenon can give rise to SI and chip reliability issues, adding decoupling capacitance is a preferred solution. Adding decoupling capacitor can be done using DECAP fillers, however, capacitance formed at very lower layers of process technology such as poly etc that too available at empty spaces not occupied by logic cells effectively leading to lesser than required capacitance values. Therefore, MIM(Metal-Insulator-Metal) capacitance layer insertion can be preferred solution. MIMCAP layers formed between topmost and one below layers of process technology, and this can be put with very high density across whole core region. Previous MIMCAP solution depended on tiled insertion of basic MIMCAP unit cell. And it need to change unit cell layout each time a change in PG grid happens affecting top two layers. Therefore, novel solution needed to address this by putting MIMCAP structure automatically by the tool according to existing PG pattern.
Ingeol Lee, Samsung Electronics
Conformal ECO Methodology and Best Practices
All chips are prone to bugs and these bugs are discovered at different stages of the IC design process. When major development is occurring in the front end phase, these bugs are easily fixed in RTL. But when RTL freeze is done, these bugs should be fixed in Post Route Netlist(PNR). This is referred as Engineering Change Order(ECO). Given the complexity of the design, manually doing an ECO on PNR netlist is difficult and often designers look to EDA tools to automate this task. Cadence Conformal is one such tool that can be used to perform an ECO. In this presentation, we will discuss the flow used to perform ECO using Conformal. We will also look into how existing Conformal LEC flow can be reused to do an ECO.
In this presentation, we’ll also discuss best known methods for running Conformal-ECO, such as mapping netlist that has multibit flops, using HFEF (Hierarchical Flatten ECO Flow) to reduce runtime on large blocks, planning out synthesis on modules that might expect to be eco (turn off cross-boundary optimization), dealing with Aborts, identify areas that could impact the quality of the eco patches (such as functional map, incomplete constraints to disable DFT, etc.).
Deekshith Krishnegowda, Marvell Semiconductor Inc.
Huy Vu, Cadence Design Systems
TSMC and Cadence Collaboration on 3D RC Extraction
Upgrading from CCD to Litmus for SDC/CDC/RDC Signoff
Noor Elahi, Texas Instruments
Using Tempus™ Timing Robustness Analysis Application
Scalable, high performance physical diagnostics pipeline
Accuracy, resolution and throughput are the most important considerations for any scan-based diagnosis method. To identify systematic failures, diagnosis is often performed on thousands of failing devices using automated simulation pipelines. This methodology, known as volume diagnosis, is a proven approach to accelerate yield learning, but is computationally expensive and sensitive to simulation time and resource availability.
Physically aware logic diagnosis greatly improves callout resolution for some defect types but presents scalability issues for large, complex processor designs. Incorporating physical layout data into simulations increases resource requirements, complexity, and overhead which significantly reduces throughput. This presentation highlights challenges and solutions needed to create an efficient high volume physical diagnosis pipeline for IBM 7nm processors in a cloud based environment. It includes insights derived from statistical analysis of results from thousands of simulations across multiple chip designs.
Key topics addressed:
1.Background on IBM’s 7nm processors and associated diagnostic challenges
2.High level physically aware diagnosis workflow
3.Maximizing logical to physical correspondence to achieve accurate physical diagnosis results
4.Scalability enhancements in the Cadence Physical Layout Server
5.Management of Cadence Physical Layout Servers in a cloud environment to minimize resource consumption and overhead
6.Insights on costs and benefits based on analysis of actual high volume results
Robert Redburn, IBM
Safety and Security Features on Tensilica IP for Automotive and Mission Critical Applications
Embedded systems deployed in safety and mission critical applications are developed to ensure they function correctly and avoid failures by detecting and managing systematic faults and random faults. However, it’s an open question whether these applications are really considered safe with incomplete security architecture. This presentation talks about the need for security in safety applications and touches on the features of Tensilica IP that help develop safe and secure embedded systems in automotive and mission-critical applications.
Sriram Kalluri, Cadence
Using Pre-Silicon Simulation for Emerging Standards
The CXL ecosystem is rapidly growing while developing design IP, verification IP, protocol analyzers, and test equipment simultaneously. If issues in products are not discovered until prototype chips are available for interop testing, product and solutions availability for companies and the ecosystem as a whole will be impacted. Meanwhile, the CXL specifications are advancing to 2.0 and 3.0 revisions, and PCIe is extending to the 6.0 revision, with next-generation products rapidly entering the planning and development stages. To keep up with the torrid pace of design innovations, there is a fundamental change in strategy to massively shift-left the verification of new CXL devices with the host IP. Intel and Cadence are working together on interop through co-simulation as a key methodology to successfully run complex cache coherent flows and validate interoperability. The CXL simulation interop demonstrates the ability to confidently build host and device IP, while also providing essential feedback to the CXL standards body.
Brian Rea, Intel
Suhas Pai, Intel
Native SEGGER J-Link debug support for Cadence Tensilica Processors and DSPs
Cadence offers some amazing IP for SoC designs. A great example is the Tensilica Processor IP, a portfolio of configurable and extensible controllers and DSPs. Combined with Cadence’s comprehensive development toolchain, it allows semiconductor companies to quickly create differentiated, domain-specific processors for their application needs.
However, until recently, there was one thing that those semiconductor companies as well as their end customers were missing out on: Native debug support by the SEGGER J-Link, the most widely used line of debug probes in the market. SEGGER J-Links have provided solid value to embedded development for over 15 years. Unparalleled performance, an extensive feature set, a multitude of supported CPUs, and compatibility with popular development environments all make J-Link an unbeatable choice.
Earlier this year, Cadence and SEGGER started the development of native SEGGER J-Link debug support for Cadence Tensilica processors and DSPs. This means that SEGGER is adding these processors and DSPs to the list of cores that are fully supported by J-Link. In turn, this enables Cadence to use the J-Link GDB Server as a native J-Link driver in their Xtensa Xplorer IDE.
This presentation highlights how this new native SEGGER J-Link integration into the Cadence Xtensa Xplorer IDE results in a much better experience for engineers developing embedded software for SoCs based on Tensilica Processors and DSPs. Attendees will learn how J-Link’s awareness of these cores lets them take advantage of much higher download and debugging speeds. The session also provides an “under-the-hood” look at the new SEGGER J-Link integration into the Xtensa Xplorer IDE. To round off the presentation, attendees will see a demo of a real-world example of debugging code on a Tensilica DSP using the Xtensa Xplorer IDE and the SEGGER J-Link.
Axel Wolf, SEGGER Microcontroller Systems LLC
Ultra-low-power implementation of Tensilica Fusion F1 processor
We present an ultra-low power single-rail implementation of Fusion F1 with on-chip SRAM generated by Xenergic’s MemoryTailor. Silicon measurements have shown the F1 sub-system with 512KB SRAM reaches 220MHz at 0.65V with a dynamic power of 19mW. The SRAM used in Fusion F1 DSP was enabled by MemoryTailor, Xenergic’s next-generation memory compiler that automatically optimizes and generates designs for the requested specifications. Silicon demonstration of the low power DSP sub-system shows that they are ideal for IoT, wakeup domains, and low power Bluetooth applications.
Dr. Adam Makosiej, Xenergic AB
Babak Mohammadi, Xenergic AB
Next Generation 224Gbps Serial Links
The high-speed I/O data rate keeps pushing for higher speed and the 224Gbps electrical serial link is critical in enabling next generation networking, compute and AI/MI SoCs. What kind of applications require 224G? What are the trade-offs when it comes to different modulation options? This presentation explores possible applications, modulation options and SerDes architectures for next generation 224Gbps electrical interfaces.
Yang Zhang, Cadence
High-Performance and Cost-Effective Die-to-Die Connectivity Enables Modern SoC Designs
System advancements in high-performance computing platforms such as CPUs, GPUs and FPGAs, AI/ML acceleration and high-speed networking are all pushing chip integration to unprecedented levels. Instead of designing these monstrous monolithic chips in a single die, the semiconductor industry is moving to developing smaller and more specialized/optimized dice (chiplets) that can be connected in a single package to provide increased computational power, expanded functionality and improved manufacturing yields.
Enabling high-performance and cost-effective die-to-die (D2D) connectivity requires careful considerations of the D2D interface as large amount of data needs to be delivered over a small die edge under stringent power and latency requirements. In this presentation, we will review the various advanced packaging technologies and D2D interface options available in the industry, and discuss how to select optimal solutions for specific use cases. Against this backdrop, Cadence UltraLink D2D PHY IP enabled on Samsung advanced process can provide a cost-effective solution for D2D connectivity in these multi-die implementations.
Tony Luk, Samsung
Practical aspects of SoC Security
Matjaz Breskvar, Beyond Semiconductor
Designing the Next Ultra Low Power Always-On Solution
Using DSPs, Hardware accelerators, and AI Engines to process vision, speech, and other sensory inputs efficiently and with low power has proven successful over the past few years. Recently, there has been a growing interest in Ultra Low Power processing for Always-On applications. These applications typically rely traditional signal processing techniques using simple microcontrollers. Throw AI in the mix, and now you have a whole new meaning to Always-On applications. In this presentation, we will highlight the trends and implementations we are seeing in the Always-On market as well as talk about the latest additions to the Cadence Tensilica portfolio to address this market.
Amol Borkar, Cadence
Microsoft Corporate 1eCAD Library Merge
Janne Vuorela, Microsoft
System Capture adoption & success at Microsoft
Naveen Konchada, Microsoft Corporation
MIPI C-PHY System SI Design Exploration
Xin Chang, META
Extraction of permeability and surface roughness using S-parameters
To evaluate the signal integrity performance of high-speed channels, both the dielectric loss and conductor loss needs to be characterized accurately. The dielectric loss is determined by the loss tangent (tanδ) of the dielectric substrates, and the conductor loss is determined by the conductivity and surface roughness of the conductors. The traditional split post dielectric resonator (SPDR) method can be used to characterize tanδ but can only be applied at discrete frequencies and requires metal-free dielectric samples. The traditional surface roughness evaluation technique requires photographing the PCB trace cross-sections, which is time-consuming and requires optical or, in the case of ultrasmooth foils, SEM equipment that is not available in many RF labs. To accurately characterize tanδ and the conductor’s surface roughness in PCBs a novel method was proposed which only requires measuring the S-parameters of coupled striplines. By relating modal attenuation factors to the ratio between the differential and common mode per-unit-length resistances, the surface roughness contribution is eliminated and the contributions of dielectric and conductor loss can be separated. No a priori information about the behavior of the dielectric properties or attenuation constant is needed, which allows capture of the arbitrary frequency-dependent behavior of tanδ. After the dielectric loss is determined, the conductor surface roughness is estimated by introducing a surface roughness model and tuning its parameters to match the measured attenuation factor. This method will allow Cadence Clarity users to accurately determine PCB parameters from only a few, simple RF measurements.
Ze Sun, Missouri University of S&T
Victor Khilkevich, Missouri University of S&T
Daryl Beetner, Missouri University of S&T
Cadence and Dassault Systèmes Partner to Transform Electronic Systems Development
Cadence Design Systems, Inc. and Dassault Systèmes recently announced (2022) a strategic partnership to provide enterprise customers in multiple vertical markets, including high tech, transportation and mobility, industrial equipment, aerospace and defense, and healthcare, with integrated, next-generation solutions for the development of high performance electronic systems.
The two companies have combined Dassault Systèmes’ 3DEXPERIENCE platform with the Cadence® Allegro® platform in a joint solution that enables companies to master the multidiscipline modeling, simulation and optimization of complex, connected electronic systems. With this new multidisciplinary solution, customers can now accelerate their end-to-end system development process while optimizing their design for performance, reliability, manufacturability, supply resilience, compliance and cost.
Dassault Systèmes and Cadence have been engaged in a multi-year collaboration with leading customers to prove this solution in a global production environment.
The collaborative virtual twin experiences integrate capabilities for electronic and mechanical product lifecycle management, business process analytics and multidiscipline electronic systems development, engineering and traceability. This holistic virtual model provides a complete, real-time view of electrical and mechanical simulation, manufacturing and supply chain execution for the product lifecycle, improving decision-making and accelerating innovation, through “what-if” studies.
Products and services are increasingly interconnected and intelligent, enabling consumers, citizens and patients to unlock more personalized, engaging experiences that improve quality of life. In this dynamic context, companies must rapidly develop electronic systems that are safe, high quality and right the first time. Mastering electronic system complexity and cost/time-to-market pressures requires collaborative innovation that unites electronics, mechanics and additional functions across the value chain.
The presentation will discuss the strategic partnership between Cadence Design Systems, Inc. and Dassault Systèmes that will revolutionize the development of high-performance electronic systems by enabling collaboration around virtual twin experiences.
Mahesh Deshpande, Dassault Systemes
Morgan Smith, Dassault Systemes
Photosensitive Glass Ceramics for Advanced RF and RF Packaging
Jeb H Flemming, 3dGS
Broadband PDK for µW SIP Design on Organic Substrate, Using Cadence AWR Microwave Office
Scott D. Sifferman, Ph.D., Systems and Processes Engineering Corp. (SPEC)
James Reimund, SPEC
Exploring Earth, the Solar System and Space with SoCs Developed using Cadence
In this presentation we provide a quick overview of several exciting Earth and planetary science investigations that are performed by JPL and NASA from UHF to Terahertz wavelengths and addressed by chipsets developed using a wide range of Cadence EDA tools (primarily the Spectre simulator). We will discuss the important role CMOS system-on-chip (SoC) technology plays in spaceborne science instruments, and the fundamental design challenges that these SoCs face in delivering the level of fidelity required for NASA’s science investigations.
Four recent CMOS SoC based instruments developed with Cadence Spectre and Innovus for upcoming NASA missions will be presented. First, the NASA WHATSUP 600 GHz emission spectrometer which measures isotopic ratios of water at Europa, Titan, and Enceladus to better understand the origins of water in our solar system. Second, an all-digital ground penetrating radar for the Mars Science Helicopter that explores subsurface deposits of ice at the Martian poles to be better understand the origins of water and ice on the red planet. Third, the NASA EMTS mission monitoring the snowpack water content in the southwestern united states to provide states accurate water resource planning during periods of prolonged drought. Lastly, the NASA SpecChip instrument which explores comets and asteroids, analyzing the gassed trapped within their icy surfaces when the solar system first formed, and giving us a glimpse into our cosmic origins.
Adrian Tang, UCLA/NASA/JPL
System Design and Analysis
Celsius for Transistor Level Thermal Analysis
Management of localized heating in ICs at the transistor level is important for avoiding temperature-related problems ranging from skewed device functionality, lifetime reduction, or even catastrophic failure. An alternative to using simplistic or empirical methods for estimating heat flow was needed to reduce uncertainty and wasted iterations for new layout and circuit designs, as well as enable wafer foundry customers to, themselves, design aggressively, taking specific packaging and other off-chip thermal factors into account.
Cadence AE’s worked with Tower to demonstrate the use of Celsius in calculating junction temperatures for various designs in our process nodes, both in the context of wafer-level testing and at the packaged component level. Built-in Celsius templates and functions were used to import and analyze test chip layouts, building realistic and comprehensive 3D thermal models that incorporated material geometry and thermal property effects such as technology cross section, die size, back-grind thickness, package type, and PCB configurations. Standard workflows were used to specify the heat sources and ambient conditions and manage simulations. Results of interest included solving the temperature distribution in power transistor arrays, their bias limitations imposed by thermal runaway, the effect of deep trench isolation, and the heating of components on insulating substrates, culminating in our determination that a key reference design's rated performance would not be limited by excessive junction temperature.
David Quon, Tower Semiconductor
A comprehensive design flow for IC and packaging for a 28GHz WiFi system
The design effort for upcoming integrated circuit and package technologies is rising because of increasing complexity. To achieve required specification values with a good trade-off of system size, current consumption, performance and costs, it is necessary to have a design flow, that enable comprehensive optimization across all components of a system. This presentation covers a system consisting of an IC manufactured in a SOI technology and an advanced packaging substrate. Both designs have been implemented within Cadence tooling. In this case Cadence Virtuoso is used for the IC and Cadence Allegro is used for the package design. To enable shifting of components from IC to package or vice versa, a tool flow was used, that enables annotation between both design tools. Using analysis tools like EMX or Clarity different variants of implementation across IC and package have been investigated and been analyzed to choose for the best solution. The system is currently in production and the presentation will also cover measurement results as well as an comparison of the simulation and measurement results.
Fabian Hopsch, Fraunhofer IIS/EAS
Wafer-scale CMP Modeling
The Chemical Mechanical Polishing (CMP) variation on a die depends on the die’s location on the wafer. For example, the post CMP thickness and/or topography variation on the center die can be very different from those on the mid-radius and edge dies. Consequently, the number of CMP hotspots and the hotspot locations can vary from die to die on a wafer. Most CMP simulation tools focus primarily on predicting the CMP effects/performance on a single die on the patterned wafer, and do not have wafer level prediction capabilities. <multiple dies for one product – wafer level simulation importance, wafer level bonding > In order for CMP simulation to be more widely used in process development and optimization, and in yield prediction and optimization, CMP simulation tools should be able to predict the CMP performance across the entire wafer.
In this paper, we present and analyze CMP data from multiple dies on BEOL Cu interconnect levels and show the wafer level effects in the polishing process. We also show wafer level modeling results for the polishing process using Cadence’s CMP simulator. We make use of an automated profile scan plotting utility in comparing and analyzing the profile scans from different dies on the wafer.
Sam Nakagawa, Globalfoundries
Substrate & PCB Advanced Innerconnects
The industry has not had many new structures in the last sixty years. Multilayers have continued to evolve with thinner materials, smaller traces / spaces as well as drilled vias. It’s been nearly forty years since the first laser-drilled microvia boards went into production.
Microslotting is a true 3D concept for interconnection by creating a routing channel (slot) in the printed circuit that then can be metallized and plated easier than microvias and allows connection to innerlayers. This allows HDI densities higher electrical performance and reliability.
Joe Dickson, Wus Printed Circuit (Kunshan) Co., Ltd
Ideation to Silicon in the Cloud
System on Chip (SoC) Architects consider design decisions based on requirements from the software developers that will target their processor-based products. Architects must consider workload-specific requirements from real-time signal processing, security & trusted firmware, to sophisticated AI/ML algorithms early in the design cycle. Thanks to flexible IP subscriptions programs, there are more options to consider than ever. Understanding differences between available compute IP Building Blocks typically involves detailed specification review and multiple meetings with IP vendors to match IP solutions to requirements. Selecting the right CPU for the given software requirements and optimizing the IP configuration has traditionally involved intensive R&D activities that range from modeling and prototyping, porting software, and benchmarking - requiring up-front investment in development tools, compute infrastructure, and months of engineering resources.
This presentation will introduce a cloud-based SoC development methodology that simplifies the front-end design process. We will demonstrate how the SoC architect can discover and compare options curated to meet their industry-specific product goals - saving weeks of ramp-up. We will show how on-demand IP selection services allow users to save months of IP evaluation by simulating exactly how the recommended IP solution will perform when running industry-standard software and benchmarks, or & even custom algorithms.
We will also discuss potential pathways towards connecting the early IP selection and configuration process with cloud-based verification of the actual SoC.
Eric Sondhi, Arm
Frank Schirrmeister, Cadence
Efficient IP integration when more than one IP defines the same module name
An industry-wide problem that is sometimes encountered when integrating RTL developed by different teams is that the same names may be used, when the content those names represent may be very different. Traditionally either 1) a single definition is used throughout the resulting design, 2) the colliding modules are uniquified to remove the collision, or 3) v2k configurations are used to map each definition to the intended hierarchy. Each of these solutions does work, but in some cases these methods delay integration and involve a measure of risk as well – risk that a collision goes silently unnoticed. Various tool features exist which together can aid in helping ensure that content within the same library is preferred over content from another library, reducing the need to use the more extreme traditional methods for handling such collisions – even when the collisions cross RTL language boundaries.
Elizabeth Woolley, Intel
Ankit Gopani, Intel
Bringing 5G to market faster: Hybrids enable earlier hardware and software verification
Want to decrease your verification time by 100x? Together with Arm Fast Models, Cadence’s Helium Studio runs up to 100 times faster in hybrid mode, giving the end user a substantial reduction in verification time and improving overall time to market. In this talk we’ll focus on a 5G design use case involving Layer 2 and Layer 3 protocol software and show how verification time was significantly shortened for an Arm-based design using hybrid mode. With the CPU subsystem running on the virtual side connected via Cadence’s Accelerated Verification IP to the interconnect, phy, memory controller and DDR on Palladium, the entire system under test runs orders of magnitude faster than pure RTL in emulation. Join this session to see how it’s done.
Eric Sondhi, Arm
Ross Dickson, Cadence
Daniel Owens, Arm
As Connectivity Speeds Soar, So Must Silicon Timelines
The demand for network capacity is increasing thanks to cloud computing, mobile edge computing, and 5G technology. Network equipment and semiconductor manufacturers need to keep up with this change by delivering ultra-high-density devices powered by cutting-edge application-specific integrated circuit (ASIC) and system-on-a-chip (SoC) solutions. To achieve aggressive time-to-market and cost-efficiency requirements, post-silicon validations are no longer sufficient. Design issues found late in post-silicon validation can cost a thousand hours of wasted effort. In addition, today’s climate will no longer support waiting until the design is baked into silicon to thoroughly validate chips. Semiconductor manufacturers need to migrate away from hardware solutions for pre-silicon verification and post-silicon validation.
To overcome these limitations, it’s time to complete silicon emulation at the Layer 1 level, and eventually, beyond. When a chipset’s entire design can be emulated, testing and bug fixes can happen in real-time. Beyond that, automation is the key to success. A testing ecosystem has been built to include pre- and post-silicon validation of physical or virtualized infrastructure and fully automated testbeds to maintain CI/CD integrity. With a simplified testbed powered by automation, testing teams do not need to learn different scripts or write million lines of code. Also, as Electronic Design Automation (EDA) emulation and testing are becoming virtual, pre-silicon testing solutions are evolving. Instead of being constrained by limited pre-purchased test ports, virtualized testing supports the scale and automated workflows required to quickly test thousand ports and easily modify the functional building blocks under test. It provides the agility and power to emulate a variety of protocols and traffic situations.
This presentation describes how Spirent Communications is partnering with Cadence to integrate automated test emulation into Cadence’s solution and to make end-to-end silicon testing, support, and services a reality. The testing solution helps customers to verify chipset design early in development cycle. The solution integrates STCv (Spirent Tester Center Virtual) L2-3 traffic generator with Cadence Virtual Network Tester Solution (Palladium Hardware Emulator). This presentation also shows how this joint solution saves costs, bridges gaps between pre- and post-silicon verification, delivers significant benefits to customers, and accelerates time-to-market.
Bob Emberley, Spirent Communications
Yufei Shi, Spirent Communications
Fast and Furious: Modeling and Simulating Analog in A Digital World
For top level design verification, analog blocks are usually the bottleneck of the simulation performance. In order to speed up the simulation, various of modeling techniques have been used for analog blocks. Sometimes it means a trade off between accuracy and performance.
Real Number Modeling (RNM) using SystemVerilog real ports is very useful for analog modeling, it simulates the top level testbench with pure digital simulator and keep the accuracy of the signals. However, there are often some number of nodes in a system that can’t be simply modeled by just a voltage or a current. These are the points where there is some level of impedance dependent interaction occurring between modules at a high enough level that it needs to be implemented for proper operation of the system level verification runs. This is exactly the point where a UDN such as EEnet can be used to effectively model the actual interaction.
A case study of top-level simulation in the Digital-on-Top environment with EEnet models is presented. These “EEnets” model voltage, current, and source resistance of the testbench drivers. The same stimulus generated for DMS simulations which use EEnets for the device pins with multiple drivers is shared for AMS simulation. Custom EEnet connect modules are added for AMS simulation.
In order to probe current on EEnet ports, a new Cadence methodology to register attributes (properties) of the IP blocks is applied in the case study design as a part of the IP creation process. Once registered, the properties are available to create probes on for viewing in debugger (waveform viewer) and can be accessed universally anywhere in the testbench. This will allow both Testbench and IP to become portable. Build and run time may increase drastically when RNM models with EEnet is brought in. SV-UDN profiling technology for Xcelium mixed signal sims from Cadence is piloted to help performance debug.
Proposed takeaways: modeling the analog behavior with EEnet makes it possible to do the design verification in a pure digital world which is much faster while still keeping the good accuracy as in the analog world by bring in the impedance for consideration. A methodology to register attributes of the IP blocks makes IP portable and reusable.
Jerry Chang, Texas Instruments
Latha Padavala, Texas Instruments
Angelika Keppeler, TI
Vijay Akkaraju, Cadence
Raj Mitra, Cadence
Benefits Of A Common Methodology For Emulation And Prototyping
The complexity of designs increases with each generation, while time-to-market schedules tighten.
Using the common methodology for Emulation and Prototyping, users are able to optimize workload distribution between verification, validation and pre-silicon software bring-up.
In this presentation you will learn the benefits of a common methodology, Hardware debug tools on emulation and Software debug tools on prototyping that will accelerate your pre-silicon product development process and optimize your shift-left strategy.
Michael Young, Cadence
Extending Jasper CSR beyond MMR verification
Noor Elahi, Texas Instruments
Kevin Barta, Texas Instruments
Aji Varghese, Texas Instruments
Helium Success at NVIDIA
Duc Le, Nvidia
Ruchir Prakash, Nvidia
Rachana Gajare, Nvidia
Xcelium Multi-Core Speeds DFT Simulation
Guoqi Lu, Lightelligence
Connecting A&D HW and SW Performers with Protium
Speeding the deployment of A&D systems is increasingly dependent on fast, assured development. BAE Space Systems develops processors that have flown billions of miles throughout the solar system. Customers add software and integrate those processors into spacecraft using prototypes developed by BAE Space Systems. The first step toward a more efficient prototyping flow was to apply the Cadence Palladium system to verifying hardware in the context of software the results of which were reported at Cadence Connect Boston in October 2020. The next step was to explore how the Cadence Protium system could be used to reduce the time to bring-up a prototype and model how a customer’s software engineer would work with that prototype. During the second half of 2021 BAE demonstrated that Protium did reduce the time to bring-up the prototype and provided a good environment in which to verify software. This presentation will report on this process and the results from the perspective of a software engineer.
Jeffrey Robertson, BAE Systems