CadenceLIVE Europe – OnDemand

Academic

Updated Cadence Portfolio Available For European Academics via Europractice

Europractice provides and supports a comprehensive range of Cadence design tools, updated on an annual basis, to European research and academic institutions for their teaching and non-commercial research.

Bryony Sweeting, Europractice
Mark Willoughby, Europractice
Clive Holmes, Europractice

End-To-End Formal Verification Of A Capability Hardware Enhanced RISC-V Processor

Capability Hardware Enhanced RISC Instructions (CHERI) extend conventional ISAs with "capabilities" that can enable fine-grained memory protection and scalable software compartmentalisation. This case study presents the formal verification of CHERI-Flute, a modified version of Flute that implements CHERI-RISC-V. To the best of our knowledge, this is the first extensive formal verification of a CHERI-enabled processor. This work exposed several previously-unknown bugs in CHERI-Flute, most of which occur in the implementation of sophisticated combinational logic for certain CHERI instructions.

Dapeng Gao, Oxford University

A 16-Channel CMOS Reconfigurable Recording Unit For Simultaneous In-Vitro Microelectrode Array (MEA) And Current-Clamp Measurements

Concurrent high-throughput patch-clamp and MEA measurements are needed to gain insight into correlation between single-cell and network dynamics. The thesis presents the design of 16-channel dual-mode recording unit for simultaneous measurements of intracellular and extracellular activities.

Asli Yelkenci, Delft University of Technology
Virgilio Valente, Delft University of Technology

Entrepreneur Showcase: Nanusens and Spiden

Nanusens is revolutionising the world of sensors with a new way to make MEMS sensors that just uses standard CMOS technology instead of custom manufacturing. This enables sensors to be made up to ten times smaller and in much greater volumes than is possible with current technology that also needs a dedicated line for each sensor product. Spiden is developing novel compact spectroscopic devices and leverages state-of-the-art machine learning methods to improve safety and quality of treatments for high-risk patients.

Josep Montanya Silvestre, Nanusens
Ennio Monteil, Spiden

Entrepreneur Showcase: SEMRON and Equal1 Labs

Current AI accelerator solutions have limited use when it comes to future applications. In this pitch and interview session, SEMRON shows how its CapRAM technology will change the edge AI world. We think that we will interact with a smart environment in the future and AI will change the world we live in. Equal1 Labs is developing the world's most-compact, most-affordable and most-scalable quantum computers using a standard CMOS process for their silicon qubits and employing Cadence tools to design their quantum processor unit (QPU) at temperatures of 4 kelvin. This presentation will describe the approach, as well as discussing the challenges and opportunities that quantum will bring. 

Kai-Uwe Demasius, SEMRON
Jason Lynch, Equal1 Labs
Imran Bashir, Equal1 Labs

Entrepreneur Showcase: MINRES Technologies and Seamless Waves

MINRES mission is to support the development of Trustworthy Software-Driven Hardware for the Intelligent Edge. Our vision is A Democratized Intelligent Edge.The bandpass Sigma-Delta, reported in this Seamless Waves presentation, is based on an LC resonator with tunable center frequency from 1.5 to 3.0 GHz and a corresponding sampling frequency from 6.0 to 12.0 GHz. For an oversampling ratio of 64, the ADC achieves the same SNDR of 37 dB and the same Dynamic Range of 45 dB over the complete tuning range. This performance is achieved for a bandwidth of 47 MHz at 1.5GHz and a Bandwidth of 93 MHz at 3 GHz. The ADC, fabricated in a 65 nm CMOS process, consumes only 13 mW from a 1.2 V supply.

Eyck Jentzsch, MINRES Technologies
Hassan Aboushady, Seamless Waves

Automotive and IP

Digital Safety Focused Verification for ISO 26262

In this paper we present a methodology for taking a design from FMEDA through to final reports using the latest fault injection technologies.

Carl Adams-Waite, Renesas
Rohitaswa Bhattacharya, Renesas

Evaluation of Legato Reliability Solution in Relation to Practical Aspects of Analog Defect Simulation Applicability in Industry

Infineon/KAI has been working on evaluating Legato™ Reliability Solutions since January 2020, using publicly available benchmark circuits from Infineon. Spectre® TFA Leadtime method is an outstanding solution for a specific type of circuit to speed up simulation time. The current solution is well suited for small and mid-size circuits, defect coverage for large circuits and full chips (e.g., full ADCs, DC-DC converters) is still a challenge regarding simulation time and resources.

Mohammad Abu Khalifa, Infineon

High Speed 112G Designs And Channel Operating Margin (COM) Dependencies
Implementing systems using 112G I/O and the dependencies on COM – Optimizing & selecting the channel parameters for superior system performance. Relevant options on the 112G PHY selection and relevant guidelines for system design of such high-speed PHY.

Wendy Wu, Cadence

Accelerating Automotive Connectivity from Infotainment to ADAS with PCI Express

New applications such as electric vehicles, autonomous driving, ADAS, digital cockpits, and in-vehicle-networking (IVN) are accelerating the deployment of automotive chips using advanced process technology all the way to 16nm, 7nm, and 5nm. With the increasing demand for high performance and bandwidth throughput, PCI Express® is playing a key role in providing high-speed connectivity solutions in all these major automotive applications. This presentation will cover the topology of these advanced automotive SoC and identifying the role of various interfaces/protocols used in these applications, with special emphasis on the role of PCI Express. We will cover applications and examples on chips designed for infotainment, digital cockpits, ADAS, in-vehicle infotainment, and v2x applications.

Thomas Wong, Cadence
Arif Khan, Cadence

FIFO Based Complex-FFT Architectures In Tensilica Connx B20

This work represents the design and TIE implementation of FIFO based flexible and fast 2n -data points complex FFT architecture. The performance of existing FFT architectures is highly limited because of the data bandwidth, especially with the shared memory. Our proposal uses four dedicated parallel read-write queues (FIFO) to improve the overall performance and throughput.

Fabian Hopsch, Fraunhofer IIS/EAS
Prasath Kumaraveeran, Fraunhofer IIS/EAS
Andy Heinig, Fraunhofer IIS/EAS

Evaluation Of Different ASIP-Configurations For An Embedded Computed Order Tracking Algorithm

The increasing size and complexity of rotating machines makes monitoring all components more critical. Therefore, this work presents a Design Space Exploration using six different Cadence® Tensilica® Xtensa® Instruction-Set Architectures and evaluates their performance regarding cycle count and power performance. Hence, a hardware-related software optimization of a computed order tracking algorithm is used and examined with a Pareto analysis at the end.

Jens Karrenbauer, Leibniz University Hannover

Computational Fluid Dynamics

A High-Quality Automated Meshing Tool For Wind Turbine Blades

At the University of Stuttgart - Institute of Aerodynamics and Gas Dynamics (IAG), an automated meshing (Automesh) tool was developed for creating high quality blade meshes. The Automesh was created by employing the scripting ability in Cadence® Pointwise®. The tool is able to create a fully-structured mesh with good boundary layer resolution and the users are able to change the parameters as desired. Studies show that mesh generation could be reduced from several days to just 30–45 minutes for a turbine blade. The talk will feature exemplary results that the generated mesh could improve the prediction accuracy of a wind turbine blade in comparison with the existing mesh obtained from a project partner.

Galih Bangga, University of Stuttgart
Thorsten Lutz, University of Stuttgart

Sailing Cadence FINE/Marine Around the Globe - CFD Simulations at finot-conq for the Vendee Globe 2024

With four wins in the nine previous editions of the Vendée Globe, finot-conq are amongst the most iconic designers for offshore racing yachts. CEO David de Premorel gives some historic perspective, and then describes the CFD work currently in progress at finot-conq for the design of the next generation of contenders.

David de Premorel, finot-conq

How Computational Fluid Dynamics extends Cadence’s Multiphysics System Analysis and Design

What is Computational Fluid Dynamics (CFD) and how does it extend the Cadence multiphysics system analysis and design capacity? Fluids are present everywhere; in our environment and in nearly all sectors of industry, as vehicles of transport and of thermomechanical and chemical energy conversion systems. The full complexity of fluid flows can only be approached through numerical CFD simulations. Examples will illustrate the potential of our current CFD systems and the variety of applications they cover. CFD today is still facing major challenges related to flow turbulence and the industrial expectations for higher reliability and efficient exploitation of High-Performance Computing. Our response to these challenges will be addressed.

Charles Hirsch, Cadence (NUMECA)

Omnis, from Meshing to Solving to Optimization, in One Single Multiphysics Environment

Engineers and designers today need many different tools for their CFD analyses. Omnis combines them all into one single environment, from meshing to solving to optimization. High-performing technology in a slick, easy-to-use interface, streamlines the workflow of all its users. From the detailed analysis of a single component (e.g. IC chip) all the way to simulating a full system (e.g. entire car), with Omnis users can combine the different physics, scale fidelity to need and create as many designs as desired. It can be fully automated, driven by AI models and optimization algorithms, and is open to third-party software through powerful APIs.

Yannick Baux, Cadence (NUMECA)

Pointwise - The Choice for CFD Meshing

Simulation during system design, before constraints are frozen, is the most opportune time to optimize and differentiate your product. High quality mesh generation is a key enabler of simulation-lead design which requires robust, efficient, and accurate simulations. The Cadence Pointwise mesh generation tool provides the flexibility and features needed to achieve faster system simulation. Based on an aerospace heritage, the Pointwise meshing philosophy focuses on mesh quality and robustness while maintaining the flexibility to drop in to a wide variety of work flows. The result is best-in-class geometry and meshing technologies which combine to provide the choice for CFD meshing.

Nick Wyman, Cadence (Pointwise)

Cloud

Accelerating EDA Productivity: The Why, What and How of the Journey to the Cloud

AI and IoT, in the cloud and at the edge, are driving a need for more rapid innovation in semiconductor devices. This talk presents examples and best practice architectures for cloud-based EDA, including use-cases inside and outside of Amazon. The talk will include an overview of how the development of next-generation products is enhanced through the use of cloud technologies. We will present performance optimization for computing, storage, and EDA workload orchestration, as well as covering how cloud enables secure collaboration in the semiconductor and electronics supply chain. We will also present examples of specific EDA workloads optimized and deployed on AWS, both internally at Amazon and at external customers.

David Pellerin, AWS

Cloud-scale Productivity without the Complexity - Have Your Cake and Eat it, Too

Today, every design team is looking at Cloud with great interest to solve their compute capacity gap and accelerate project Turn Around Time (TAT). However, transitioning EDA and CAD flows to cloud can be complex, requiring thoughtful decisions about cloud architecture, data management, IT retraining, infrastructure setup, security, to name just a few. This session will discuss Cadence platform to overcome cloud complexity. We’ll also uncover industry’s newest breed of cloud products that are allowing designers to enjoy their familiar on-prem design environment and yet enjoy all the great benefits of secure, scalable and agile cloud. All the goodness of cloud without the effort and delays involved in adopting and optimizing the right cloud environment. Have your cake and eat it too!!

Ketan Joshi, Cadence

Developing Scalable AI Inference Chip with Cadence Flow in Azure Cloud

d-Matrix, a cutting-edge startup, is building a first-of-its-kind, in-memory computing platform targeted for AI inferencing workloads in the datacenter. A pioneer in digital in-memory computing for the datacenter, d-Matrix is focused on attacking the physics of memory-compute integration using innovative circuit techniques, an approach that offers a path to massive gains in compute efficiency. With focus on AI innovation, the team chose full Cadence flow; and rather than setting up on-prem compute infrastructure, the design flow leveraged Azure Cloud. This session will discuss how d-Matrix setup a productive Azure cloud infrastructure running Cadence flow, the lessons learned and the key success factors that led to delivering first AI chip within 14 months.

Farhad Shakeri, d-Matrix
Andy Chun, Azure

Designing Planet-Scale Video Chips on Google Cloud

Recently, Google announced a custom video chip to perform video operations faster for Youtube videos. Google’s TPU series of chips are also well-known for accelerating AI/ML workloads. These are just a couple of examples of chips designed by Google engineers. Google hardware teams have been leveraging Google Cloud for chip design for a few years, and this presentation highlights the benefits of using Google Cloud for chip design. Semiconductor customers can accelerate their time to market by leveraging the elasticity, scale and innovative AI/ML solutions offered by Google Cloud. Many large enterprises are choosing Google Cloud for their digital transformation. Google Cloud provides a highly secure and reliable platform, infrastructure modernization solutions, and best-in class AI platform for the Semiconductor Industry. We will share relevant aspects of cloud (Compute, Storage, Networking, Workload Management, reference architecture) that enable high-performance chip design. We will discuss how typical verification and implementation flows on GCP can benefit by migrating to cloud, with specific examples for RTL simulation and full-chip analysis. We will also detail how customers can get started on their cloud journey. Every cloud journey is unique. We will share how we leverage Google Cloud internally for designing chips such as the Argos video chip. The Google Hardware team will share their journey with GCP with key learnings and benefits of migrating to Cloud. We will also share the challenges faced, and discuss verification/design workload migration and best practices.

Sashi Obilisetty, Google
Peeyush Tugnawat, Google
Jon Heisterberg, Google

Custom Analog

Cadence Virtuoso And Spectre Technology Update

Join us for a technology update and roadmap presentation for the Virtuoso Design and Spectre Simulation Platforms. Three major topics will be covered, Virtuoso ADE Product Suite, Virtuoso Layout Suite, and the Spectre Platform. We will point out highlights from the latest ISR releases in each of the areas covering new team design features for layout, reliability extensions in the Virtuoso ADE Product Suite, and the new Spectre FX Simulator among other topics.

Stewen Lewis, Cadence
Joy Han, Cadence
Yuval Shay, Cadence

From The Best Usage Of Advanced Virtuoso Functionalities

This presentation focuses on the role of analog layouters and the synergy that can take place between them and the Virtuoso environment. Virtuoso® Layout Editor software (specifically, ICAdvm – IC Advanced Methodology solution) can be seen as the companion of the layouter. We can even consider the layouter as the companion of Virtuoso, in that the Virtuoso environment can be seen as a whole virtual world. There is a way to bring innovation in the role of the layouter, even for technologies where we are not in the “Moore’s law” run, but in the “More than Moore” law. This innovation resides in the smart usage of Virtuoso functionalities.

Stéphane Clin, STMicroelectronics
Florent Parmentier, STMicroelectronics

Introduction to an Automated PDK Verification Flow: "XVerifFlow"

“XVerifFlow” introduces an automated PDK verification flow to check the PDK functionality for default or any pcell parameter combination for different X-FAB technologies. It performs the comparison of pre and post-layout simulation, netlist extraction, and sanity check. It explains shows how the flow is integrated with Cadence® Virtuoso® design environment and uses PVS tool suit. It gives flexibility to user to automatically generate any Quantus Extraction Solution (analog extracted, dspf, smart view) and provides comparison of different netlist.

Smriti Joshi, X-FAB
Heng Kiat Jing, X-FAB
Melanie Wilhelm, X-FAB

A Novel Approach Of Integrated Electro-Thermal Simulation For Automotive Applications

This work investigates the Cadence® Legato™ Reliability Solution for electrothermal (ET) evaluation of chip design. Such an integrated flow is introduced first in comparison with a conventional flow, which often employs external multi-physics simulator solving the heat equations. Integrated ET flow has shown its advantage in error free data handling and improved efficiency, as data transfer between electric simulator and thermal simulator is cumbersome manual handling.

Chong Jin, ams
Alexander Steinmair, ams
Bernd Schuscha, Graz University of Technology

A Novel Verification Methodology to Predict Temperature Behaviour of Analog Trimmed Parameters Using Virtuoso ADE and Spectre Simulator

The presentation “A Novel Verification Methodology to Predict Temperature Behavior of Analog Trimmed Parameters Using ADE and Spectre Simulator” describes how to run trimming for an analog circuit over montecarlo corners when a transient simulation is needed and how to verify the functionality of the trimmed circuit with respect to corner analysis and in particular versus temperature. The proposed approach allows to exploit all the ADE feature for statistical analysis. A few are used in the presentation to verify the functionality of the circuit. The presentation goes through the complexity of the trimming procedure and the need to predict the behavior over temperature of the trimmed device so to guarantee the best trimming procedure for the sample at the ATE. 

Valerio Gennari Santori, STMicroelectronics
Marco Neri, Cadence

Common Denominator Tiles (CDT) and Embedded Metal Lines (EML)

Common Denominator Tile (CDT) and Embedded Metal Lines (EML) is an approach to advanced node layouts. It presents a solution to layout challenges at advanced nodes caused by increased Design Rule complexity and number. This methodology is based on our experience with several advanced nodes and provides many benefits like less frequent DRC runs, multi-patterning ease, density checks, etc., while being a tool-assisted and friendly approach.

Gaurav Masiwal, IC Mask Design
James Telfer, IC Mask Design

Analog Fault Injection for Functional Safety Analysis Using Legato Reliability Solution

Fault injection testing is a highly recommended method for the verification of hardware safety requirements for ASIL C and D products (ISO26262-5 Table 11). In this presentation we show how we practically implemented fault injection simulation with Cadence Legato™ Reliability Solution for the pre-silicon verification of safety metrics of a functional block. We cover the modeling of faults, setting up the simulation bench for fault simulation, selecting a representative faults sample, and generating the metrics from the simulation results.

Patricia Joris, Melexis Technologies
Yurii Toporov, Melexis Technologies

Electro-Thermal Co-Simulation for Electromigration Analysis with Voltus-Fi

Self-Heating induced effects such as accelerated wear out due to electromigration is a growing concern among designers. The Voltus™-Fi SHE flow allows to address this without excessive overdesign. In order to take into account thermal coupling and additional heat paths, the Spectre-Voltus-Fi flow has been redesigned for that purpose. It will be discussed how that flow works and how this is applied to GlobalFoundries Silicon Photonics technology 45spclo.

Hendrik Mau, GlobalFoundries
Ingo Kuehn, GlobalFoundries

FLUID PCELL: A New Way To Create Layout

In this presentation we will discuss the design of complex POWER MOS (Array of VDMOS) devices using FLUID SKILL PCELL along with the ABUTMENT mechanism provided by the Virtuoso® design platform, which both have significantly enhanced the layout productivity. With this methodology, based on the FLUID editing capability of SKILL PCELL, the interactivity with the user is much improved and changes are managed more easily within the SKILL code. In sum, the turnaround time for one development cycle is reduced by 50% compared to standard.

Sylvain Coquel, STMicroelectronics

Selfheat Management of 22FDX MMW Design

In this talk, we show the GlobalFoundries selfheat aware electromigration flow steps using Cadence tools. We also talk about how to check the back end of line electromigration reliability on 22FDX RF/MMW Design.

Shanthi Siemes, GlobalFoundries
Ingo Kuehn, GlobalFoundries

Aging Profile Simulations with Virtuoso ADE Product Suite

In advanced nodes circuit aging simulation is an inevitable part of pre-silicon verification, ensuring circuit performance and functionality is sustained for the complete product lifetime. State-of-the-art aging simulation can consider only one certain stress scenario of a circuit at a time, i.e. the simulation outputs only the aging impact of one certain operating mode, supply voltage, temperature etc. This is a bottleneck for reliability assessments of circuits seeing multiple critical stress scenarios during their lifetime. This presentation shows how to overcome the limits of state-of-the-art aging simulation by enabling so-called aging mission profile simulations. During mission profile aging simulations multiple stress scenarios are simulated and finally combined, yielding the total impact of all stress scenarios at the circuit performance and functionality. The aging mission profile simulation capability is an important feature of modern reliability simulation tools, allowing design and reliability engineers more precise and realistic aging simulations. The application is highly relevant for RF and power management systems, automotive designs and digital high-performance products in which circuits typically operate at various critical operating conditions and operating states. In this presentation we will examine how aging profile simulations can be run with commercial circuit design software. Based on generic design examples all important features and capabilities of the profile simulation will be demonstrated.

Leonhard Heiss, Intel
Andreas Lachmann, Intel
Clement Melen, Intel
Reiner Schwab, Intel

Mixed Signal

Mixed-Signal Physical Design For Advanced Nodes Technologies Using OA Based P&R Tool

One challenge of mixed-signal physical design is to merge data of two totally different worlds of design-technique: Digital synthesis and analog design. This presentation will point out how the two worlds are getting closer and what can be done to close existing gaps. The target of this session is to give some hints how the gap between P&R and analog design environment can be closed.

Wolfgang Auchter, Intel

Automation and Reuse of Analog/Mixed-Signal RF Layout Components in Nanometer Nodes

Analog and mixed-signal RF IC components are inevitable in order to enable fast communication at high frequencies. Designing them, however, is still a very complicated task with many different steps to finally form a piece of silicon from a given specification. So-called generators are one supporting tool to overcome today's limitations. Generators automate analog/mixed-signal and RF building block layouts. As there is not a “one size fits all solution,” design and automation should be considered together. Thus, a scheme will be presented that helps with decision-making on “manual” design vs. generator automation types.

Benjamin Prautsch, Fraunhofer IIS/EAS
Uwe Eichler, Fraunhofer IIS/EAS
Helga Dornelas, Fraunhofer IIS/EAS

Improvement of Productivity for MS Physical Design Implementation by Embedding a P&R Routing Engine into the Analog Design Environment

The complexity in the back-end implementation of the advanced node technologies has been increased. To achieve a good productivity in AMS Design there is a strong need for a Digital Auto Router which respects the existing Advanced Nodes Design Rules. Target of the session is to point out, how a standard cell design has been successfully created with Placement Engine in Analog Environment, and auto-routed by using Digital Router Engine embedded in the Analog Environment.

Wolfgang Auchter, Intel

Mixed-Signal Verification Technology Update – Advanced Debug Capabilities and Performance Boost

This session will update you on the latest Cadence mixed-signal flow enhancements, in the areas of advanced debugging capabilities and performance boost. The session concludes with software demonstrations explaining, how the new Cadence® SimVision™ Mixed-Signal Debug (SimVision MS) option can reveal the invisible portions of Analog/Mixed-Signal Test Benches (TB) and help with your SoC mixed-signal verification. If you face mixed-signal design and verification challenges or simply want to learn more about these topics, please join this session.

Joy Han, Cadence
Andre Baguenir, Cadence

Getting Your $$$ from Verilog-A

Verilog-A is very powerful but often the way to wrote code that works in the way the analog solver it design is not. This presentation will go over common mistakes and how to deal with them so that the simulator is happy. You will also learn on how to write Verilog-A code or analog blocks within Verilog-AMS files that work in harmony with the the analog solver.

Presentation PDF file also contains Verilog-A functions examples that are not Cadence origin and are kindly made available by Peter Grove.

Peter Grove, Renesas

Active Filtering Based on EEnet Technology

In a first part we will present NFC solution context and necessity to have efficient analog IP modelization to avoid time simulation to be unsustainable. Afterward, we will expose how we developed active filters with ideal operational amplifiers using EEnet methodology and evaluate results compared with Z transform filter methodology, and analog Simulation reference.

Guillaume Durand, STMicroelectronics

Are We Done Yet? How to Get an Overview on The Status of The Analog Verification

Owing to the heterogenous nature of analog circuits with its continuous parameters, the status and quality of an analog regression is often hard to judge. While we have clear metrics in Cadence vManager™ solution for digital and mixed signal regressions, there was thus far a gap for analog circuits. To ensure the requirements are really met, it is necessary to consider operating conditions. In this talk, we will show how we bring the operating conditions along with the requirements from our specifications into Cadence Virtuoso ADE Verifier without any manual interaction. This way we ensure full specification coverage and tracking of results. Automation is done through Cadence-provided API functions.

Angelika Keppeler, Texas Instruments
Jerry Chang, Texas Instruments
Mayank Jain, Texas Instruments
Robert Stranghoehner, Texas Instruments

Unified Testbench For AMS, DMS And Schematic

A unified testbench for DMS, AMS and schematic has been implemented with Cadence® Virtuoso ADE Suite. The DUT is driven by discrete stimulus in verilog AMS, and logic and wreal signals are converted into electrical domain with customized conversion modules to keep accuracy. All the probed signals are processed in the discrete domain with assertions in SystemVerilog. The testbench can be easily configurate for schematic and model by maestro design variables. And by running parallel corner simulations, the schematic and model can be compared directly. In the end, the model is precisely validated against the schematic, and using model for testbench developing significantly reduce the working hours.

Yi Wang, Renesas

Rapid Design and Verification of Mixed-Signal Systems Through Virtuoso Suite and MATLAB Integration

Cadence and MathWorks integrated workflows for design, visualization and verification of mixed-signal systems.

Ganesh Raj Rathinavel, MathWorks
Andrew Beckett, Cadence

Liberate MX Evaluation for CCS, CCSP, CCSN Characterization of X-FAB RAMs and ROMs

The X-FAB new approach for RAM and ROM characterization utilizes the flexibility of Cadence® Liberate™ MX manual characterization flow (also called the full custom flow) and power of the in-house characterization scripts. The key benefit of Liberate MX and Spectre® simulation platform is full support of advanced CCS, CCSP, CCSN liberty formats for X-FAB RAM and ROM IPs. The advantage of the X-FAB characterization flow with Liberate MX is easy adoption for different technologies, different RAM and ROM IPs and low efforts for setting up production characterization flow.

Artur Tvozhydlo, X-FAB

PCB

System Design Platform Technology Update – Pervasive Performance and Productivity

Saugat Sen, Cadence

A Journey Around ST Automotive Design Evolution And Cadence Platform Solution

Package development techniques like co-design for system connectivity management, design methods for supporting new design concepts, checks for validating new structures and, design and electrical modelling link, must evolve rapidly to sustain new challenging product specification. EDA world is fast adapting to this transformation. From our automotive digital BGA development experience, some examples can be mentioned to confirm Cadence IC packaging design platform, since many years, is evolving to efficiently support automotive digital products and offer new solutions for package development.

Cristina Somma, STMicroelectronics

Automatic Verification and Report Generation For Daisy-Chain Test Structures In A Chip/Package/PCB Co-Design Environment

We have implemented a novel, enhanced daisy chain toolbox inside our Infineon chip/package/PCB co-design flow, which will be presented in this session. 

Thomas Brandtner, Infineon
Martin Benisek, Infineon
Marc Dittes, Infineon

How To Reduce Design Error Risks For Complex 3D BGA/LGA Package Module

This paper will present the overall package substrate design flow used in STMicroelectronics around the Cadence® Allegro® platform, from die data to substrate manufacturing, with all the key steps to guarantee a success of the first run: front-end data import, technology management (substrate and assembly), substrate routing, design checks (substrate and assembly rules, electrical constraints, connectivity) and manufacturing data export.

Claire Laporte, STMicroelectronics
Jean-Francois Caillet, STMicroelectronics
Didier Signoret, STMicroelectronics
Laurent Schwartz, STMicroelectronics

Improving Design Productivity In Allegro And OrCAD PCB Editor Technologies

Put routing at the side. Printed circuit boards have routing on top and bottom and on layers in between. However, miniaturization requires also metallization at the side of the outline. Edge plating and castellation is used to connect the board without connectors and improving the thermal and EMI behavior of the system. Learn about this technique and how to do it in your design in OrCAD® or Allegro® PCB Editor.

Dirk Mueller, FlowCAD

Accelerating PCB Design Cycles With In-Design Analysis

In this session we will discuss how Sigrity™ Aurora and Sigrity Topology Explorer can help you accelerate the PCB design cycle. The In-Design Analysis features of Aurora allow designers to run simulations early in the design process, increasing the confidence in the design and catching issues where they can be most easily addressed, while Topology Explorer allows both more in depth analysis, and constraint capture.

John Phillips, Cadence

RF Design

AWR Technology Update - Analysis And Work Flow Integration For Advanced RF Systems

Join our RF expert as he presents how the latest release of Cadence® AWR Design Environment® (Version 16) platform supports the development of RF front-end components such as power amplifiers, and advanced antenna/arrays with ready access to Cadence Clarity™ 3D Solver and Celsius™ Thermal Solver, delivering unconstrained capacity for the analysis of large-scale and complex RF systems directly from within the RF design environment. Furthermore, groundbreaking cross-platform work flows from AWR software to Cadence Allegro® PCB Designer, Virtuoso® System Design, and Virtuoso® RF Solution platforms delivers up to a 50% reduction in turnaround time compared to competing RFIC, MMIC, module, and PCB design solutions.

Andrew Wallace, Cadence

Virtuoso RF Solution Technology Update

The Virtuoso® RF (VRF) design flow brings together the schematic editor, layout implementation, parasitic extraction, EM analysis and RF circuit simulation, along with integrated layout versus schematic (LVS) and design rule checking (DRC) in a single flow. This presentation covers the latest enhancements into the Virtuoso RF platform.

Ron Pongratz, Cadence

77 GHz 28FDSOI LNA Full EM Characterization Through Virtuoso RF and EMX

In this presentation, ST Microelectronics shows the results of evaluating the Virtuoso RF Solution/EMX flow on a fully integrated 77GHz 28FDSOI LNA for automotive radar. The full integration of this new RF flow within the Virtuoso® platform, with the availability of an efficient 3D planar EM solver such as EMX, allows you to correctly characterize all the passive components of a whole IC (inductors, transformers, connections, moncap and resistors) without any partitioning of the layout itself. Moreover, the creation of an extracted view, with the S-parameters from the EM solver automatically stitched within the schematic view, allows for the creation of a Spectre® RF testbench; it is thus possible to easily evaluate the impact of EM parasitics on the overall performance of the IC. A very good agreement with measurements confirm the accuracy of the flow.

Kevin Morot, STMicroelectronics
Raphael Paulin, STMicroelectronics
Enrico Sacchi, Cadence

On-Chip Inductor Synthesis

State of the art on-chip inductor design lags behind compared to other IC components with respect to layout generation and simulation models. The work to be presented explores many aspects of on-chip inductor design, partly by using Cadence® EMX, a newly available field solver by Cadence. The proposed design flow automation makes use of PCell-based layout generation, the simulation with EMX, and model fitting to optimize custom inductor layouts for the desired electrical properties.

Stefan Kosnac, EXTOLL

Matching Network Synthesis ​ for Virtual Antenna Technology ​with Cadence Microwave Office

The evolution of the Internet of Things (IoT) and communication networks require small and multiband antennas. The objective of this presentation is to discuss a method capable of embedding Virtual Antenna™ into an IoT device in a fast, easy, and systematic way. With the help of Cadence Microwave Office matching network synthesis capabilities.

Alejandro Fernandez, Ramon Llull University
Nuria Ramos, Ramon Llull University
Jose Luis Pina, Ramon Llull University

Digital Implementation and Signoff

Digital Design and Implementation 2021 Updates

Latest innovations from the Digital Design and Implementation group relating to power savings, advanced node coverage, machine learning and multi-chipset flows will be presented.

Vinay Patwardhan, Cadence
Rob Knoth, Cadence

Differentiated and High Quality Library Solutions Using Liberate Trio

The current diverse semiconductor product usage is pushing the boundaries for circuits to derive better PPA than ever before. This is leading to development of newer unconventional circuits, which need thorough validation to identify corner failure mechanisms. This paper discusses similar Liberate™-based capabilities that help in detecting remote issues and expedite productization of high quality new differentiated circuit designs.

Dhavalkumar Atulbhai Bhalodia, Samsung
Rajeela Deshpande, Samsung
Abhishek Ghosh, Samsung

How to Handle Successfully the Hierarchical Implementation of a 14M Instance RISC-V Based HPC Design in 22nm FD-SOI

In this presentation we will cover topics like partitioning, power analysis, timing correlation and signoff using a hierarchical approach for a design in 22FDSOI with 14M placeable instances at a target frequency of 1GHz.

Jithin Visakh, Fraunhofer IIS
Chenming Shao, Fraunhofer IIS

Memory-On-Logic Stacking For Multi-Core SoCs At Advanced Nodes

The CMOS scaling trend is now changing, in view of limitations caused by the very small features of modern-days devices. 3D integration represents one of the most promising innovative strategies for continued scaling. Building on the Cadence tools capabilities of performing 3D-aware place and route, we have developed a methodology to expend the level of 3D awareness into signoff timing analysis.

Giuliano Sisto, Cadence
Dragomir Milojevic, imec
Rongmei Chen, imec
Geert Van der Plas, imec

A Vectorless-Based Ecosystem For Voltage-Sensitive Critical Path Identification

In this presentation, we will show STMicroelectronics experience with Tempus™PI and the capability of such innovative solution in the contest of an advanced node SoC design activity.

Francesco Alessio, STMicroelectronics
Lorenzo Arrigoni, STMicroelectronics
Andrea Barletta, Cadence
Giuseppe Panzera, Cadence

System Design

A Reference Flow for Chip-Package Co-Design for 5G/mmWave Using Assembly Design Kit (ADK)

The design effort for upcoming integrated circuit and package technologies is rising because of increasing complexity in production. To cope with that situation it is essential to reuse pre-qualified elements for handle complexity. For package technologies this becomes more and more apparent. Looking at the requirements for 5G applications in a radio frequency up to 60 GHz for package technologies it is no longer feasible to start from scratch. So it becomes more and more import to use prequalified elements for a technology. This paper deals with the implementation of RF-structures for manufacturing and characterization and the how to cover the interaction in the system across IC and different package levels with dedicated tooling.

Fabian Hopsch, Fraunhofer IIS/EAS
Andy Heinig, Fraunhofer IIS/EAS

Reimaging 3D FEM Extraction with Clarity 3D Solver

Join us to learn and apply the latest innovations in the full-wave Cadence Clarity™ 3D Solver to analyze your next-gen system design. Deep dive with us into the fully distributed architecture of the Clarity 3D Solver that enables you to extract large and complex packages and PCBs using hundreds of cores in the cloud or your on-premises farm — all while taking as little as 8GB memory per core.

Robert Myoung, Cadence

System Analysis of a Transmission Board Using Sigrity PowerDC and BBS Tool

In this presentation, we will explain how power supplies on the transmission board have been simulated with Sigrity™ PowerDC™. From the largest power supply with a maximum current load of 25A to the smallest power supply with only 0.15A current draw. As a finishing touch we will show how we used the BroadBand SPICE (BBS) tool for TDR analysis.

Pepjin Kampf, Grass Valley

Modelling and Simulation of Differential Chip to PCB Interface up to 40GHz Using 3D-FEM Solver

An essential requirement in transforming the integrated chip's performance to system functionality is the interconnection within a module. At high mm-wave frequencies, the integrated chips show tremendous performance with respect to the frequency limits. However, the interconnection forms the bottleneck in realizing such systems, and modeling the interconnects is challenging. This presentation focuses on modeling and optimizing an integrated chip to PCB interface with bond wires using a 3D-FEM Solver to analyze broadband matching. In general, 3D-FEM solvers are used to model the integrated chips and the interconnections separately. Cadence Clarity™ 3D solver offers a solution to 3D electromagnetic (EM) simulate the interconnects for PCBs and system on IC. The complete interface from chip to PCB will be built up and simulated within the Virtuoso® RF module.

Lokaja Bonagiri, Cadence

Verification

Improving Simulation Regression Efficiency Using Xcelium Machine Learning Technology In Functional Verification

This paper discusses various ways of improving verification throughput: Ranking and the new Cadence® Xcelium™ Machine Learning (ML) based technology. Both methods aim at getting comparable coverage in less CPU time by applying more efficient stimulus. Ranking selects specific seeds that simply turned out to come up with the largest coverage in previous simulations, while Xcelium ML generates optimized patterns as a result of finding correlations between randomization points and achieved coverage of previous regressions. Quantified results as well as the pros and cons of each approach are discussed in this paper at the example of three actual industry projects.

Deepak Narayan Gadde, Infineon
Sebastian Simon, Infineon
Djones Lettnin, Infineon

Achieving Code Coverage Signoff on a Configurable and Constantly Changing Design Using JasperGold Coverage Unreachability App

This presentation will go through our approach of achieving code coverage signoff on a highly configurable design using both simulation based and formal tools. We will go through the initial challenges of using the JasperGold® Unreachability App and it benefits in achieving the final goal of code coverage signoff. The presentation will share the results from an active project to explain the importance of formal analysis in code coverage closure.

Mayur Desai, Broadcom

Accelerating Simulation Of ATPG Scan Tests With Xcelium Multi-Core

Verifying DFT SCAN structures is quite an important task, the results of which can affect future iterations of the synthesis flow. The final step of SCAN verification is simulation of Modus ATPG Verilog testbenches. Unfortunately, simulation takes a lot of time especially if serial format is used. Usually it can take plenty of days or even weeks. Therefore, test acceleration becomes a significant topic. Xcelium™ Multi-Core offers opportunities for such acceleration with quick and easy integration into existing flow and scripts. In this presentation we present the results of research which aims were to evaluate possible acceleration ratios for different SCAN ATPG tests using various CPU configurations.

Arseny Komlev, RC Module

Verifying Register Maps With JasperGold CSR: How Formal Compares To UVM

The Register Map is the core of a Digital Design. The Register Map contains the configuration of the device; if we are not able to write or read the configuration in which the device is then we cannot guarantee its functionalites. This is why we need to verify the RegMap exaustively and find a methodology to guarantee the silicon will be bug free on the RegMap. The goal is to verify a RegMap (already verified using UVM) using only Formal Verification (JasperGold CSR) and compare the results in terms of effort required, code and functional coverage, time spent to find/detect a bug, bugs found.

Davide Sanalitro, STMicroelectronics
Edoardo Bollea, STMicroelectronics

Emulation as Verification Speedup Platform

The increasing complexity of SoCs designs nowadays causes significant challenges to allow for the use of realistic use cases to verify the designs early enough before the tapeout. We leverage different platforms with different level of modeling to support the targeted uses cases. These are Boot Rom, OS based use cases, very long use cases which need few tenths of seconds of real run time and need the use of the ASIC RTL to cover clocks, startup, duty cycling of the chip and interaction with external devices (PMIC, External Memories). Palladium® offers interesting opportunities to gain more powerful verification use cases with an interesting debug capabilities and speedup while having an accurate representation of our design. The use of Palladium along with FPGA Platform and simulation helps us to appropriately address our verification and debug requirements and achieve better results.

Khaled Nsaibia, u-blox
Berk Olcum, u-blox

Efficient System Stress and Randomization Through PSS Based Concurrency

This presentation describes the work that has been done to integrate the various IPs to run concurrently. System level validation often involves having many of the same flows run at IP level in addition to global flows. A single platform integration framework is required to allow us to combine multiple IPs together for added benefit, while scheduling the different operations. PSS was the framework chosen for this integration. We will demonstrate the value added by running different IPs concurrently, while providing the option to randomize and bias each IP’s activity and randomizing thread assignments. Through this, we have increased system stress beyond what each individual IP can provide, with a solution that is easily scalable.

Jeremy Elman, Intel
Gassan Tabajah, Intel
Sima Bakst, Intel