CadenceLIVE China – OnDemand
Automotive Cloud and Verification
George Geng Cadence
Fault Injection Techniques Using Xcelium Fault Simulator
Xiaobin Qi Cadence
Cloud-Scale Productivity Without the Complexity - Have Your Cake and Eat It, Too!
This session will discuss Cadence platform to overcome cloud complexity. We’ll also uncover industry’s newest breed of cloud products that are allowing designers to enjoy their familiar on-prem design environment and yet enjoy all the great benefits of secure, scalable and agile cloud.
Rui Pan Cadence
What is “Shift Left” and Why Do Hardware Engineers Suddenly Care So Much About Software
Learn why it is now mission-critical to do software development and bring-up earlier for every company designing electronics. Understand how this effort ties directly to the evolution of electronics entering a new phase – Intelligent System Design. Electronification of everything is a megatrend, and the introduction of intelligence in devices is providing crucial differentiation. Systems companies are building proprietary semiconductor chips, optimized for purpose and form factor. And, software brings it all together. However, time-to-market pressures are even greater, as functional complexity is exploding. Hear first-hand the challenges and approaches to early software development, system bring-up, and verification and learn how you can incorporate a shift left methodology utilizing Cadence products throughout your SoC design cycle.
Sophie Fan Cadence
Dynamic Duo: A Common Methodology for Emulation and Prototyping
Jingwei Liu Cadence
Accelerating Co-Verification Productivity by Using Palladium Emulator as a Leverage
This presentation gives insight to some of the co-verification methodologies supported by Cadence Palladium Emulator. As a leverage, it is used to reduce time of simulation platform and improve greater debuggability of FPGA platform. These performance improvement methodologies were selectively experimented on many projects in ADI and the encouraging results and details of one project are shared in this paper.
Shawn Zhang Analog Devices
MulticoreWare ML Experience with Cadence Vision and AI Processors
Bo Hu MulticoreWare
Enable the High-Performance System with Cadence GDDR6 IP
Water Zhang Cadence
Introduction to Tensilica Vision P1 DSP
Cadence Tensilica Vision DSP系列产品是在业界公认的图像处理，视觉处理及AI处理的最佳选择。在这个研讨会上，我们会和大家一起分享下市场的趋势以及对Vision DSP提出需求的应用。然后，我们将向大家介绍1款新发布的产品 Vision P1,针对对功耗极其敏感的CV和AI的应用。
Wei Wang Cadence
Introduction to Tensilica Floating DSP
Ming Xu Cadence
Custom IC Design
Digital Front End and Signoff
Front-End Design Solutions to Deliver the Lowest Power Products to Market
Rob Knoth Cadence
Tempus PI and Voltus
Hitendra Divecha & Rajat Chaudhry Cadence
通过Tempus Power Integrity实现仿真和实测中关键时序路径的一致性研究
When we use traditional timing signoff (STA) with a proper margin or derate for voltage variations, it will help us to cover most scenarios of real silicon. But as chips are designed larger and larger, features of hardware and software increase more and more, we see some critical cases will lead timing to fail caused by IR drop, even if IR analysis is under criteria. Now, most of our designs such as AI chips are designed on 12nm, 7nm or less, with a 3DIC interposer. IR drop analysis is more and more complex and important. Meanwhile, timing analysis with IR drop requests. Tempus Power Integrity provides a true signoff solution for concurrent IR drop and timing, which helps us find the real critical timing path with voltage-sensitive.
Jinjin Yu Enflame
Full Chip Stylus Genus iSpatial Flow Improves Implementation Efficiency
This paper introduces Stylus Genus iSpatial flow implementation on 54 million gatecounts, 28nm FDSOI, Arm core design. First, iSpatial flow and Stylus flow are introduced. Stylus iSpatial flow provides unified and predictable flow from synthesis to PR in common user interface and consistent setup&report. Then, Stylus Genus iSpatial flow building method is proposed. After proper setup, new flow is run and compared to original flow. By iSpatial engine, synthesis does most place optimization job with better PPA, then data passes down to Innovus seamlessly for place incremental optimization and following steps in Stylus platform. At last, summary result is given between iSpatial flow and regular flow.
Glen Ge NXP Semiconductors
Arm Cortex-A75 PPA Benchmark Based on GF 12LP+ Platform
In this paper, it is illustrated that with all the powerful FIP and SRAM listed above, ARM Cortex A75 cores are implemented successfully using Cadence Stylus flow (Genus for synthesis, Innovus for place and route, Voltus for power signoff and Tempus for timing signoff). During the implementation stage, several powerful techniques that Innovus supports help improve overall QoR impressively.
Ning Luo GlobalFoundries
Synthesis Flow Optimization with Genus iSpatial and Mixed Placer for 16nm Design
Our chip is a NPU SOC with more than 400 million instances, hundreds of soft blocks, more than ten thousand macros, thousands of clocks and the chip area is more than 600 mm2 using TSMC 16nm technology which all give big challenge to the EDA tools and design resources. In this paper, we will share what we do with Genus i-spatial flow, Innovus i-spatial flow and our customized synthesis flow.
Genus i-spatial gives better correlation and acceptable run-time than our former flow, result in a good QoR in PR stage. In addition, during the early stage of the project, with Innovus mix-placer flow, we successfully achieved accurate evaluation without the participation of physical design team, saves our working resources.
Liming Zhao H3C
Mixed Placement在Genus iSpatial中的结合应用
在7/5nm工艺下instance呈现翻倍增长，同时面临更高性能和数据吞吐量的需求，传统的EDA Flow不太容易满足后端设计要求。通过Mixed Placement,在项目初期没有Floorplan的条件下时，在Genus 中通过predict_floorplan 调用Innovus 快速做一次Mixed Placement，生成一个Floorplan 出来。在设计早期就可以进行iSpatial流程，可以及早的发现设计的Congestion 问题，而且可以提前预测preCTS阶段时序，便于更早的进行代码优化。
Xincan Ling ZTE
Efficient Synthesis Methodology for Large-Scale Design
• Challenge of Large Scale Design: Capacity/Runtime/resource/PPA Challenge
• Strategy for block level Synthesis: Synthesis criteria for different strategy, Alchip block level synthesis strategy
• Hierarchical Synthesis Flow: ETM flow VS ILM flow, Alchip Hierarchical flow
Cui Cui Alchip
Innovus 21.1 – Innovation Unleashed For Best PPA
Vinay Patwardhan Cadence
Optimization of I/O Flop Clock Latency in Innovus Implementation System for Better Top-Level Timing Closure
Brenda Peng NVIDIA
Accelerate MMMC Timing Closure with Signoff Opt Design with Innovus Implementation System
At the advanced process nodes, the increase number of operating modes and process-voltage-temperature(PVT) corners brought the increase of signoff mode, which makes final timing closure is fast becoming the bottleneck of tapeout. In response to this question, the use of signoffOptDesign(SOD) convergence method, directly in-design fix based on signoff results by invoke Qrc and Tempus tools, compared with traditional convergence method, can be effective reduce the turn-around time(TAT), thereby accelerating the the overall convergence of the design. In actual projects, through comparing the traditional timing convergence method and SOD timing convergence method, it is found that the timing convergence using SOD can reach almost a consistent result with lesser TAT required by the traditional convergence method, which effectively reduces the overall design convergence interval.
Jinwei Zeng ZTE Sanechips
Power Stripe Design for Best Routing Track Utilization
This paper proposes “track-based power stripe design” to achieve best routing track utilization for power stripes. First, power stripe “on-track” conception is introduced -- When regular wire is routed legally on neighbouring track, there’s no space waste between power stripe and regular net. For “on-track” power stripe, it should have both specific width and correct location, otherwise, there’s either “track-waste” or “width-waste”. Then in Innovus, one procedure is developed to check all power stripes. Problematic stripes are highlighted for review and optimization. After that, several chips/submodules are checked as example. With “track-based power stripe” re-design, hundreds to thousands routing tracks can be saved without punishment of total stripe width.
Next, one further topic is discussed. For each layer, if total stripe width is not changed, which stripes width can achieve high routing-track efficiency and which stripe width can achieve best efficiency? Analysis is done and result shows piecewise relationship because of wide metal space rule. Result table is first-hand guideline to design high efficient power stripe, but in real case, more factors especially IR drop should be co-considered to decide final stripe strategy.
At last, “track-based power stripe design” methodology is summarized.
Ting Gao NXP Semiconductors
Automatic IR Drop Fixing with Innovus Implementation System
With the help of Cadence's newly IR Aware Full Flow, the author uses local P/G stripe addition, timing aware IR drop fixing, IR aware placement etc. to avoid and address IR drop issues all through the PR flow. These techniques significantly improve the efficiency of IR drop hot spot fixing and greatly accelerate the convergence of IR drop problems. IR Aware Full Flow saves designers much more time in getting a better PPA result and is of great use to the design process of IC physical implementation.
Jian Wan ZTE Sanechips
Adaptive Body-Bias Technique to Improve Glitch Power
With CMOS feature size scaling, the increased chip density and the operating frequency have made the power consumption a great concern in VLSI design. The power cost can be classified as dynamic and leakage (static) power consumption. As the contributor to the dynamic power, a glitch is an undesired transition that occurs before intended value in digital circuits. A glitch occurs in CMOS circuits when differential delay at the inputs of a gate is greater than inertial delay, which results in notable amount of power consumption, especially for designs with deep logic levels. In this work, based on our library study results by using the Cadence tool Joules, we found that adopting the adaptive body bias (ABB) technology can have great glitch suppression without performance degradation, which have been demonstrated by two cases implemented by Cadence Innovus with GF 22nm FDSOI technology. It is suggested that more than 30% glitch power can be reduced compared with the zero body bias (ZBB) mode. Additionally, from the Cadence Voltus results, the serious dynamic IR drop due to the high activity induced by the glitch can also be relaxed obviously.
Shaofeng Guo GlobalFoundries
PCB Design and IC Packaging
System Design Platform - Pervasive Performance and Productivity
Saugat Sen Cadence
Overcoming Thermal and Stress Signoff Challenges for 2.5D/3D-IC Design with Celsius Thermal Solver
Xiaohui Zhong Cadence
基于Power DC 的电热协同仿真测试案例介绍
随着系统功能的日益复杂和速率快速提升，对于PCB的通流压力越来越大，常规的评估通流能力方式遇到了瓶颈，不能满足产品日益增加的电流需求。需要探索一种新的仿真评估方法，通过电热联合仿真来准确评估由于PCB引起的温升，并借助系统散热边界条件来提升通流能力是一种可行的方式，本文基于Power dc 进行了大量的仿测对比工作，验证了仿真方法工具的精确程度，并利于热交换系数成功导入系统边界条件，极大的提升了PCB的通流能力。
Liqiang Meng ZTE
随着云计算，云数据中心以及5G带来的数据传输量和速率的不断攀升，高带宽，低功耗并行接口将逐渐成为大型数据传输和运算的关键接口。超高的速率给整个DDR通道，包括并不限于芯片，封装基板、PCB和连接器的设计和仿真带来了挑战。本议题将讨论6400Mbps LPDDR5高速通道设计带来的新挑战以及应对方式，并讨论如何使用Cadence® Sigrity™技术和Cadence® Clarity™ 3D Solver来解决这些挑战。
Tonghao Ding H3C
Shorten PCB Design Cycle Time Using Synchronous Team Design
Allegro PCB Symphony Team Design-Cadence推出的多人协同功能，支持多人协作布局、设规则、布线和交互式联合审查。复杂，高速的PCB，而相差无几的周期对于不同的工程师团队协作提出很高要求。Symphony可以确保团队高效运作，灵活地配置专业工程师资源，使不同的功能和不同经验的工程师实时、并行在同一设计中协作，完成PCB板设计和检查，极大地节省PCB设计周期，加速产品上市。
Alice Wang Inventec
Manufacturing Rules-Driven to Shorter Product Design Cycle
DFM means Design For manufacturability which is executed by Manufacturing site to review if the PCB design can meet the requirements for mass production according to some manufacturing rules, but doing DFM check in PCB design phase can help PCB designer mitigate some violations of manufacturing rules before submission to Manufacturing site, which can improve efficiency, save time for PCB to PCBA end to end and avoid cost waste during the whole process. The topic is to introduce how DFM works in Cadence.
Bin Zhu Schneider Electric
The Rigid-Flex Design and 3D EM Simulation Based on Allegro Technology and Clarity 3D Solver
Cadence® Allegro™提供了一个基于Multi-zones的刚柔结合板设计平台，在Allegro工具中，我们可以轻松地在一个设计文件中完成刚柔结合板的设计。而在Cadence® Clarity™3D Solver中，我们可以直接将Allegro完成的刚柔结合板设计导入，无需进行额外的结构编辑，并进行整板的三维全波电磁仿真，从而避免了对设计的切割及后期S参数结果的级联，在充分考虑刚板和柔板之间的耦合及阻抗不连续性的情况下，快速得到了高精度的仿真结果。借助Allegro和Clarity完整而成熟的设计和仿真流程，我们得以快速高效地完成刚柔结合板的设计和EM性能签核。
Xuanjiang Shen Omnivision
From EDA to SDA: The Latest Update on Multiphysics System Analysis of Cadence
Ben Gu Cadence
Is 3D FEM Solver Scalability Ready to Go Big? Clarity 3D Solver Cloud
Kezhou Li Cadence
Omnis, from Meshing to Solving to Optimization, in One Single Multiphysics Environment
Steve Yan Cadence
Optimizing 2.5D/3D-IC Design with Efficient Power and Signal Integrity Analysis
This presentation developed a novel methodology to design and qualify HBM memory system performance to meet JEDEC standards based on solid SI/PI simulation technology with complete consideration of Simultaneously Switching Noise(SSN) effects on such massive parallel I/O performance. Also, technical simulation results have been rigorously verified with Lab measurement to proven the simulation technology’s capability can meet our production requirement.
Yongsong He Enflame
基于Clarity 3D Solver和Virtuoso RF Solution的IC和封装电磁协同仿真
Virtuoso RF解决方案是一种基于Virtuoso平台的系统感知设计解决方案。借助VRF流程，我们可以轻松地将PKG物理设计导入到Virtuoso中，并将合并了IC和PKG的设计调用Clarity 3D Solver用于电磁（EM）分析。 Cadence®Clarity™3D解算器是一种全波三维电磁（EM）仿真软件工具，用于设计IC，封装，PCB，系统及其不同组合的关键互连。我们在Clarity中合并了IC部分和PKG部分，并进行了EM协同仿真，从而获得了IC和PKG之间的耦合干扰，精度很高。借助Clarity生成的S参数模型，我们可以实现系统感知的仿真，并在流片之前对关键规格进行良好的评估。
Kai Kang UNISOC
高速高频信号的三维场建模需要足够的精度及更快的效率 - Sigrity, Clarity 3D Solver介绍
In this paper, we will test the real channel performance after calibration, and use the Sigrity clarity 3D to simulate and fit it, observe the simulation accuracy and efficiency, and give the actual case suggestions.
Gang Huang EDADOC
A Complete Scalable Solution for SoC Low-Power Verification
As SoC is becoming more and more complex, the SoC low-power design has more and more power domains and power states which brings a big challenge to the SoC low-power functions for a qualified verification . This paper focus on the dynamic verification for the low-power functions. To verify the low-power functions completely, it’s necessary to active the power-on devices under test (DUT) randomly when changing the low-power states randomly in one pattern with complete checkers and coverage. This paper would introduce a complete scalable solution and platform for the complex low-power verification with little effort.
Yuqi Xu UNISOC
Brief Introduction of PSS with Perspec System Verifier Used in Qualcomm SDC SoC DV Team
This paper elaborates the common basic flow used in Qualcomm SOC projects, from register automatic flow, coherence issues, and performance scenarios. With simple registers’ description files and Project configuration tables and SOC test configuration tables which design intent are captured, tests can be generated even before RTL is ready. The advantage of reuse and efficiency is so obvious, Verification engineers just need to update these chips' tables according to new projects or some of low level drivers, tests can be generated automatically, It reduces times engineers take to create tests by manual no mater with C or SV cases, With thorough abstract and system level design intents been captured and reviewed across teams, bugs can be found at earlier stages, with randomized scenario generation scheme, all possible corners can be targeted efficiently. Along with Cadence Perspec which fully supports the PSS released by Accellera, scripts for pre and post-processing are also required as a complete methodology.
Fuli Yang Qualcomm
Pre-Silicon Validation with Cadence Palladium Z1 and Protium X1 Platforms
•FPGA Prototyping Challenges
•Palladium Z1+ Protium X1 co-verification Solution
Xiaobo Fan Stream Computing
Jiajun Liang ZTE Sanechips
本文介绍了验证管理工具vManager，通过python调用vAPI接口与企业级的产品需求管理系统Microsoft TFS和用户数据后台对接 ， 实现了从自动创建验证需求框架（即vPlan）, 自动执行回归验证，自动提取验证结果反标Microsoft TFS中的需求状态，自动提取验证结果呈现到验证看板的自动化验证管理全流程。本方案旨在自动化、规范化地实现验证需求到vPlan的同步，验证回归状态和覆盖率数据的实时汇总，实现验证的高效率与高透明度，需求跟踪达到滴水不漏。该方案还采用了vManager最新一代的High Available模式，可实现跨地域的多团队合作与数据共享，并部署了多引擎验证工具的包括Xcelium, JasperGold和Palladium的验证管理，实现多维度的验证数据汇总。目前该方案已经部署真实研发环境中，为vManager在国内比较领先的应用，为业内提供跨地域合作+多个仿真引擎的大规模自动化验证方案提供非常有价值的参考。
Yu Zhi ZTE Sanechips
How to Use Indago Debug Platform to Improve Debugging Efficiency
ARM CHINA, the leader of IP supplies, is keep working on releasing IP product with more functions and efficiency, which takes us great effort in IP design verification. With the help of Indago, a debug tool from Cadence, verification engineers are able to locate and resolve issues during debugging. Indago supports several levels of debug mode for users with different application situations. Engineers are able to do waveform review, design circuit inspect, low power states and even proceed offline breakpoint debug after simulation. We will present the experiences of Indago practical application in presentation.
Lunping Guo Arm
SoC Verification Solution Based on Palladium Accelerated VIP
Our company has developed a set of scenarios for verifying MIPI or using MIPI to verify internal image processing modules based on MIPI AVIP, which has achieved dozens of times of acceleration ratio and greatly improved the simulation speed. As well as using AMBA AVIP to simulate and monitor the behavior of related modules which can be used to get the pre-netlist power data and performance data .It has made an important contribution to the functional verification and power/performance optimization of the chip.
Jianzhong Zhang ZEKU