Pushing Verification Throughput With Cadence
Umer Yousufzai, Cadence
Sign-off clock gating verification using JG SEC
Clock gating (CG) techniques are broadly used in the industry mainly in order to save power or for security aspects. Yet, it’s hard to verify the correctness of the CG logic -how can someone be sure that the clock won’t be gated when it shouldn’t? The common method to verify it is to run functional regressions with the CG cells. Nevertheless, this doesn't fully guarantee that the addition of the CG has no harmful impact, as long as it is based on dynamic simulation methods we are bound to coverage limitations and vectors reachability states. This abstract describes how to leverage Sequential Equivalence Checking (SEC) app to compare two designs and prove their sequential behavioral equivalence end to end. On this technique one design is defined as the golden model and the second one as the implementation. In this case, these two are identical except that the clock is free running on the golden model, while logically for any given input vector the output should be acting the same. The goal is to prove that under any condition, both designs behave equally and the low power optimization has no functional impact on the design. Using JasperGold SEC application we were able to formally prove that CG logic inserted to the implementation design was equivalent to the golden design with free running clocks. In this presentation we will show the results of applying the aforementioned method in various modules. The presentation will explore the challenges identified alongside implementation examples and relevant implications to the verification infrastructure. Demonstrate the various issues and counterexamples found as well as analyze the runtime and non-convergence issues. Finally we present a breakdown of this method and a comparison with the simulation based flow.
Netanel Miller, Texas Instruments
Verification Reuse Taken to the Next Level with Portable Hardware-Software Interface
Since the release of Accellera’sPortable Stimulus Standard (PSS) in 2018, industry adoption has been growing steadily, with public reports of major productivity and efficiency gains. However, one of the key promises of a portable stimulus language is only recently materializing into a solution, with the expected release of PSS version 2.0. This is the ability to encode lower-level device programming logic in terms that are truly portable across verification environments, from IP, to subsystem, to full-chip, and across verification platforms, from Virtual-Platform, through simulation and emulation, all the way to post-silicon. The inclusion of general procedural-language constructs, together with built-in support for memory management, register descriptions, and various read/write operations, allow PSS models to program and control hardware devices directly. Given such descriptions, tools generate test code that drives testbench transactors or embedded processor cores, and possibly a mixture of these, with the push of a button. And with that, full reuse is achieved from the top-level test intent, all the way down to low-level implementation. Over the past year, early-adopter PSS users have been deploying these capabilities in real project settings. Their experience provides both positive indication of the validity of the solution, as well as some practical takeaways.
Matan Vax, Cadence
Verification of a Multi-language Components - A case study: Specman E Environment with SystemVerilog UVM UVC
Verification of a complex SOC today demands the use of Verification IPs from diverse sources. The ability to utilize available verification components and embed them into an existing Verification Environment, which often consists of different languages, isof great importance. The Accelera UVM-ML Open Architecture provides the ability to assemble and co-simulate components that are written in different languages. Nevertheless, some synchronization aspects -such as sequences alignment and data transport between those components -are left for one's determination. In this paper, we demonstrate a common case for Multi-language necessity: a SOC that is generally verified with a Specman E environment that utilizes an SV UVM Verification Component from an external vendor. In the implementation of this system, we deployed a mechanism for data and bilingual sequence synchronization. In this project, we also deal with a dilemma: In what circumstances is it better to translate (or rewrite) code to another language, rather than combine it in a different language environment.
Eran Lahav, Veriest Solutions
Verifying real firmware flows in Pre-Silicon simulations
One of the challenges we face today is to verify real firmware flows in Pre-Silicon simulations and find HW Bugs related to FW flows in Pre-Silicon. In this presentation, we will share with you how we connected the Design Verification functions written inSpecman with FW functions written in C, using automation that encapsulates the C to e / e to C connectivity using MACROs enabling a simple user interface.
Omer Glazman, NVIDIA