DIS01 : Accelerating the Power Signoff Challenges in 7nm Complex Multi-Million SoC Designs in Voltus IC Power Integrity Solutions
CadenceLIVE: India- Digital Implementation and Signoff
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DIS02 : A Cookbook for Aggressive Area Reduction Strategy on Arm Cortex-A55 CPU Core Using Cadence Implementation, Power, and Signoff Solutions
CadenceLIVE: India- Digital Implementation and Signoff
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DIS03 : Chip Reset Methodology for Optimal Digital Design Implementation and Signoff
CadenceLIVE: India- Digital Implementation and Signoff
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DIS04 : Clock Tree Synthesis Using Flexible Structured CTS for Complex Clocking, High Divergence, and Highly Rectilinear Floorplan
CadenceLIVE: India- Digital Implementation and Signoff
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DIS05 : Custom Clock for Network on Chip Architecture
CadenceLIVE: India- Digital Implementation and Signoff
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DIS06 : Extending Power, Performance, and Area (PPA) Leadership using Machine Learning
CadenceLIVE: India- Digital Implementation and Signoff
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DIS07 : Leakage Power Recovery of a High-Frequency MIM-Based Processor Design Using Tempus TSO-ECO Signoff Solution
CadenceLIVE: India- Digital Implementation and Signoff CadenceLIVE: India- Digital Implementation and Signoff
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DIS08 : Technology Update - Digital Full Flow Innovation Delivering Design Excellence
CadenceLIVE: India- Digital Implementation and Signoff
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DIS09 : Tempus Power Integrity: A True Signoff Solution for Concurrent IR Drop and Timing at Lower Nodes
CadenceLIVE: India- Digital Implementation and Signoff
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DIS10 : Tempus SmartScope-Based Hierarchical Analysis and Closure
CadenceLIVE: India- Digital Implementation and Signoff
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