1 : Guest Keynote: Cadence and Academia: From Transistors to Systems with Computational Software
CadenceLIVE: India-Keynote
Watch Video2 : Keynote: Computational Software for Intelligent System Design
CadenceLIVE: India-Keynote
Watch Video1 : Guest Keynote: Cadence and Academia: From Transistors to Systems with Computational Software
CadenceLIVE: India-Keynote
Watch Video2 : Keynote: Computational Software for Intelligent System Design
CadenceLIVE: India-Keynote
Watch VideoCADI01 : A Common Platform for Generalizing, Capturing, Analyzing, and Exporting Custom Structures Across PDK and Designs Using Circuit Prospector
CadenceLIVE: India - Custom and Analog Design: Implementation
Watch VideoCADI02 : An Automated and Reliable Methodology to Check Shielding of Sensitive Signals in Analog Layouts
CadenceLIVE: India - Custom and Analog Design: Implementation
Watch VideoCADI03 : CKE (Concurrent Layout Editing, a New Advanced Methodology for the Next Generation of MSot Smart Power (BSD) Design
CadenceLIVE: India - Custom and Analog Design: Implementation
Watch VideoCADI04 : Design-Driven Analog Layout Methodologies Using Virtuoso XL 18
CadenceLIVE: India - Custom and Analog Design: Implementation
Watch VideoCADI05 : Developing Correct-by-Construction Standard Cells Using Virtuoso Pin Accessibility Checker
CadenceLIVE: India - Custom and Analog Design: Implementation
Watch VideoCADI06 : Improving Design TAT and Reliability by Adding Electrical Awareness Early in Design Cycle
CadenceLIVE: India - Custom and Analog Design: Implementation
Watch VideoCADI07 : Technology Update - Thinking Beyond The Chip
CadenceLIVE: India - Custom and Analog Design: Implementation
Watch VideoCADI08 : Virtuoso Environment-Based P&R for Standard Cell - Based Layouts
CadenceLIVE: India - Custom and Analog Design: Implementation
Watch VideoCADV01 : Advanced Methodology for Accurate EM-IR Analysis in Voltus-Fi XL
CadenceLIVE: India - Custom and Analog Design: Verification
Watch VideoCADV02 : Functional Verification of a PMU
CadenceLIVE: India - Custom and Analog Design: Verification
Watch VideoCADV03 : Mismatch Analysis and Tuning for Analog IP with Virtuoso Variation Option
CadenceLIVE: India - Custom and Analog Design: Verification
Watch VideoCADV04 : Methodology for Accurate Design and Verification of High-Speed Delta Sigma ADC's with Virtuoso ADE Assembler, Spectre X, and Voltus-Fi Technology
CadenceLIVE: India - Custom and Analog Design: Verification
Watch VideoCADV05 : Multi-User Flow in Analog DV Using Setup Library Assistant and Virtuoso ADE Verifier
CadenceLIVE: India - Custom and Analog Design: Verification
Watch VideoCADV06 : Streamlined Flow for Enabling Instance-Based Multi-Technology for Mixed Simulation Designs
CadenceLIVE: India - Custom and Analog Design: Verification
Watch VideoCADV07 : Taking the Analog Simulation Performance to the Next Level Using Spectre X Simulator
CadenceLIVE: India - Custom and Analog Design: Verification
Watch VideoCADV08 : Technology Update - Spectre Simulation Platform
CadenceLIVE: India - Custom and Analog Design: Verification
Watch VideoDFD01 : Advanced Static Low-Power Verification Topics and Methodology
CadenceLIVE: India- Digital Front-End Design
Watch VideoDFD02 : Better Predictability and PPA with Genus iSpatial Technology
CadenceLIVE: India- Digital Front-End Design
Watch VideoDFD03 : Efficient Handling of Super Under Drive Corner with Genus iSpatial at Lower Tech Nodes
Watch VideoDFD04 : Embracing Conformal ECO Designer Over Indigenous Manual ECO
CadenceLIVE: India- Digital Front-End Design
Watch VideoDFD05 : Extending Innovation with Joules RTL Power Solution and Conformal Formal Verification Solution
CadenceLIVE: India- Digital Front-End Design
Watch VideoDFD06 : Improved TOPS per Watt in Computer Vision Products Through PD Power Optimizations
CadenceLIVE: India- Digital Front-End Design
Watch VideoDFD07 : Modus DFT – Solving the Physical Problems of Test
CadenceLIVE: India- Digital Front-End Design
Watch VideoDFD08 : Novel Methods for Achieving High Coverage with Low Test Time Using LBIST at SoC Level
CadenceLIVE: India- Digital Front-End Design
Watch VideoDFD09 : Power-Aware Scan Architecture Using Low-Power Gating Compressor
CadenceLIVE: India- Digital Front-End Design
Watch VideoDFD10 : Synthesis Methodology to Achieve Best-in-Class Performance and Power on Complex Low-Power Designs
CadenceLIVE: India- Digital Front-End Design
Watch VideoDIS01 : Accelerating the Power Signoff Challenges in 7nm Complex Multi-Million SoC Designs in Voltus IC Power Integrity Solutions
CadenceLIVE: India- Digital Implementation and Signoff
Watch VideoDIS02 : A Cookbook for Aggressive Area Reduction Strategy on Arm Cortex-A55 CPU Core Using Cadence Implementation, Power, and Signoff Solutions
CadenceLIVE: India- Digital Implementation and Signoff
Watch VideoDIS03 : WATCH ON DEMAND Chip Reset Methodology for Optimal Digital Design Implementation and Signoff
CadenceLIVE: India- Digital Implementation and Signoff
Watch VideoDIS04 : Clock Tree Synthesis Using Flexible Structured CTS for Complex Clocking, High Divergence, and Highly Rectilinear Floorplan
CadenceLIVE: India- Digital Implementation and Signoff
Watch VideoDIS05 : Custom Clock for Network on Chip Architecture
CadenceLIVE: India- Digital Implementation and Signoff
Watch VideoDIS06 : Extending Power, Performance, and Area (PPA) Leadership using Machine Learning
CadenceLIVE: India- Digital Implementation and Signoff
Watch VideoDIS07 : Leakage Power Recovery of a High-Frequency MIM-Based Processor Design Using Tempus TSO-ECO Signoff Solution
CadenceLIVE: India- Digital Implementation and Signoff CadenceLIVE: India- Digital Implementation and Signoff
Watch VideoDIS08 : Technology Update - Digital Full Flow Innovation Delivering Design Excellence
CadenceLIVE: India- Digital Implementation and Signoff
Watch VideoDIS09 : Tempus Power Integrity: A True Signoff Solution for Concurrent IR Drop and Timing at Lower Nodes
CadenceLIVE: India- Digital Implementation and Signoff
Watch VideoDIS10 : Tempus SmartScope-Based Hierarchical Analysis and Closure
CadenceLIVE: India- Digital Implementation and Signoff
Watch VideoISVP1 : Accelerating SoC Verification Signoff Using SNR/DTR Enhanced Regression Flow
CadenceLIVE: India- IP/Subsystem Verification: Performance and Smart Bug Hunting
Watch VideoISVP2 : Accelerating Verification Productivity by Harnessing Latest Xcelium Simulator Performance Improvement Methodologies
CadenceLIVE: India- IP/Subsystem Verification: Performance and Smart Bug Hunting
Watch VideoISVP3 : Code Coverage Metric Signoff and Integrating JasperGold Coverage Unreachability (UNR)App Flow in vManager Simulation Regression Environment
CadenceLIVE: India- IP/Subsystem Verification: Performance and Smart Bug Hunting
Watch VideoISVP4 : Experience of Using Formal Verification for a Complex Memory Subsystem Design
CadenceLIVE: India- IP/Subsystem Verification: Performance and Smart Bug Hunting
Watch VideoISVP5 : New Paradigm for Improving Verification Productivity, Emerging as an Aided Workforce, Using Xcelium Save and Restart Feature
CadenceLIVE: India- IP/Subsystem Verification: Performance and Smart Bug Hunting
Watch VideoISVP6 : Technology Update - Pushing Verification Throughput with Cadence
CadenceLIVE: India- IP/Subsystem Verification: Performance and Smart Bug Hunting
Watch VideoISVP7 : Verification of LPDDR5 High-Speed Memory Controller and PHY Using Cadence Denali VIP
CadenceLIVE: India- IP/Subsystem Verification: Performance and Smart Bug Hunting
Watch VideoPCB01 : Accurate S-Parameter Extraction and Analysis for Rigid-Flex Board with Wirebonded CoBs
CadenceLIVE: India- PCB Design and System Analysis
Watch VideoPCB02 : Achieving High Throughput and Design Efficiency with Allegro Productivity Toolbox Solution
CadenceLIVE: India- PCB Design and System Analysis
Watch VideoPCB03 : Cadence AWR Design Environment: A Simulation Platform for RF and Microwave Designers
CadenceLIVE: India- PCB Design and System Analysis
Watch VideoPCB04 : Modeling and Simulation Challenges of DDR5/LPDDR5 Interfaces and Enabling DFE Techniques Using Sigrity Technology
CadenceLIVE: India- PCB Design and System Analysis
Watch VideoPCB05 : Optimizing Gate Drive Circuits for Automotive Applications Using PSpice A/D
CadenceLIVE: India- PCB Design and System Analysis
Watch VideoPCB06 : Signal Integrity Analysis of HBM2E-Based Silicon Interposer Using SystemSI
CadenceLIVE: India- PCB Design and System Analysis
Watch VideoPCB07 : Technology Update - Data-Driven System Design and Analysis
CadenceLIVE: India- PCB Design and System Analysis
Watch VideoPCB08 : USB 3.0 Electrical Compliance
CadenceLIVE: India- PCB Design and System Analysis
Watch VideoPCB09 : Zig-Zag Routing for High-Speed Signals 20GBPS
CadenceLIVE: India- PCB Design and System Analysis
Watch Video1 : Accelerating ATPG Simulations Using Xcelium Multi-Core Simulator
CadenceLIVE: India- SoC Verification: Advanced Verification Methodology
Watch Video2 : Enhanced Test Bench Architecture for Robust PHY Verification Using PHY Monitor
CadenceLIVE: India- SoC Verification: Advanced Verification Methodology
Watch Video3 : Invited Paper Faster Regressions Using Xcelium with Machine Learning
CadenceLIVE: India- SoC Verification: Advanced Verification Methodology
Watch Video4 : New Parallel/Incremental-Build Paradigm Leading to More than 11X Gain with Parallel Compile and 7X with Parallel Elaboration Using Xcelium Features
CadenceLIVE: India- SoC Verification: Advanced Verification Methodology
Watch Video5 : Technology Update - Pushing Verification Throughput with Cadence
CadenceLIVE: India- SoC Verification: Advanced Verification Methodology
Watch VideoSDVE01 : GSP Emulation with Palladium Platform and Prototyping with Protium Platform
CadenceLIVE: India- System Design and Verification: Emulation and Prototyping
Watch VideoSDVE02 : Improving Firmware Validation Productivity and Debug Efficiency Using Palladium Z1 Platform and Indago Debug Analyzer
CadenceLIVE: India- System Design and Verification: Emulation and Prototyping
Watch VideoSDVE03 : SoC Firmware Debugging Tracer in Emulation Platform
CadenceLIVE: India- System Design and Verification: Emulation and Prototyping
Watch VideoSDVE04 : Technology Update - Pushing Verification Throughput with Cadence
CadenceLIVE: India- System Design and Verification: Emulation and Prototyping
Watch VideoSDVF01 : Acceleration of Coreless SoC DV Using PSS with Superior Coverage on Multi-Link PCIe Subsystems
CadenceLIVE: India- System Design and Verification: Flows
Watch VideoSDVF02 : Advanced Mixed-Signal Modelling Methods Using System Verilog for Efficient System-Level Verification: Challenges, Opportunities, and Enablers
CadenceLIVE: India- System Design and Verification: Flows
Watch VideoSDVF03 : Efficient Fault Injection Methodology for ASIL-D-Compliant Automotive SoCs
CadenceLIVE: India- System Design and Verification: Flows
Watch VideoSDVF04 : Quicker Verification Signoff for Nested Networks-on-Chip (NOCs) in Complex SoC
CadenceLIVE: India- System Design and Verification: Flows
Watch VideoSDVF05 : Technology Update - Pushing Verification Throughput with Cadence
CadenceLIVE: India- System Design and Verification: Flows
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