A Flexible Lockstep Architecture for ASIL Compliant DSPs and Controllers
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Designing a Geolocation Solution Addressing IoT Power and Cost Challenges
Many view location tracking to be one of the killer apps for IoT. But advanced logistics, transportation, smart city and smart factory applications strain the current class of solutions, often designed with smartphone or vehicle navigation in mind. These solutions fall short in terms of power consumption, cost and coverage indoors. Based on advanced signal processing algorithms and a hybrid device/cloud architecture, Nestwave has developed a low-power geolocation solution that eliminates the need for a dedicated positioning chipset. When combined with the efficiency of the Cadence Fusions DSP , geolocation performance is improved with substantially reduced power consumption.Power to cost
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Latest Trends in Memories and Cadence Offerings
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Legato analog fault simulation for safety coverage: a case-study
In this case-study, fault simulation is performed on an analog buffer by injecting random faults on device level. These randomly generated faults are grouped into different categories, while the simulation results can be splitted for different failure groups that gives an insight of the circuit behavior. As an end result, the outcome of the simulation gives the safety performance of the buffer for the considered fault groups which is defined by automotive standards. This results can be used to rate the functional coverage and safety performance of this particular analog block. Legato reliability solution is used with its Rapid Adaption Kit (RAK) as a guideline for fault simulation in this case-study. The design example for analog buffer is designed on TSMC 180 nm BCD technology.
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Not All 112G/56G SerDes Are Born Equal - Select the Right PAM4 SerDes for Your Application
Hyperscale computing continues to be the main driver for very high-speed SerDes, and 112G/56G is a key enabler for cloud data center and optical networking applications. 56G connectivity is particularly important for 5G infrastructure deployment, both in baseband and remote radio head systems. After being first to market in 2019 with silicon-proven 112G-LR SerDes on TSMC 7nm technology, we have now expanded our high speed portfolio to include PPA-optimized 56G-LR in TSMC N7/N6 processes to address the connectivity needs of the 5G infrastructure and AI/ML market and have all the building blocks to accelerate the adoption and deployment of cost-effective 100G and 400G networks as well as a trajectory to a 25.6T switches. However, not all PAM4 high speed SerDes are born equal. In this presentation, we will share with you the various flavors of LR, MR/VSR and XSR high speed SerDes and where they fit best in the end application space. You will also learn the tradeoffs between data rate, power, performance, area, insertion loss, and flexibility of use to help you decide the right PAM4 SerDes for your next design.
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Physical Implementation Methodology of Arm Cortex-A76AE Processor
The bulk of this presentation will focus on physical implementation of the Cortex-A76AE processor core using advanced features of Cadence RTL to GDS2 digital implementation tool chain in 7nm.
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RF/Microwave Design in the Era of Connected Cars
This presentation examines several case studies in which RF/microwave engineers have used design software to address a range of challenges in developing high-frequency components and systems for various automotive applications and supporting antenna systems. These case studies include the use of 3D finite element EM analysis to accurately model a wireless tire pressure sensor, matching impedance network development for a low-noise amplifier (LNA) design for an SDARS receiver, and the use of EM analysis to perform an electromagnetic compatibility (EMC) simulation of an automotive navigation/audio system.
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Radar Technology for Advanced Driver Assist Systems
By implementing radar technology over the 76-81GHz spectrum, advanced driver assist systems (ADAS) enable smart vehicles to alert and assist drivers in a variety of functions, from smart cruise control and collision avoidance to self-parking. These automotive radar applications use the millimeter-wave (mmWave) spectrum to exploit more bandwidth for greater resolution and object detection. However, higher frequency propagation comes with greater path loss, as isotropic free-space attenuation is inversely proportional to wavelength. In addition, along with this additional path loss, as wavelengths get smaller, physical processes such as diffraction, scattering and material penetration loss make the channel properties of mmWave bands significantly more challenging. This presentation examines the radar technology commonly found in ADAS systems and highlights a design example that illustrates how a basic frequency-modulated continuous wave (FMCW) radar system operates. The combined use of system, circuit, and EM tools to overcome the challenges in mmWave (77 GHz) automotive radar design and phased array antenna development is discussed.
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The Evolution of Sensing, Computing and Architecture Going from ADAS to Automated Driving
The level of automation of a vehicle is the key driver of the E/E architecture and the electronic content of a car. It’s obvious that future cars will be equipped with more computing power, AI-based systems, car-to-car communication technology, high-bandwidth Ethernet networks, and digital cockpits. Radar, Lidar and Camera are the key sensors to enable fully autonomous driving. However these sensors still need to be significantly improved in terms of resolution, power consumption, safety, form factor and cost but will also evolve to address new compute architectures. All these new technologies will dramatically increase the complexity of electronic systems which require to integrate more functionality on a chip, rather than on a PCB to provide the performance, safety and reliability in a small form factor device. As a result, a new class of high-performance System-on-Chip (SoC) and/or System-in-Package (SiP) is needed to process all sensor data and fuse them together to enable vehicles to become “aware” of their surroundings. While some high-end automotive SoCs have been already designed in 7nm some companies are preparing already their next-generation process technology at 5nm. Foundries claim that 5nm provides about 20 percent faster speed or about 40 percent power reduction and is perfectly suited for the next generation of automotive processors. Cadence's Automotive solutions can help you to enable such highly integrated systems that can make cars safer and more reliable. This talk provides an overview on automotive trends and the implications for SoC and System enablement for Sensors and Advanced Driver Assist Systems (ADAS).
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Ultra low power processor subsytems with customized memories in 22FDX
The presentation details how a Tensilica, i.e., Fusion F1, based system is realized in 22 FDX from GlobalFoundries. The SoC operates at an aggressively scaled single supply voltage of 600 mV, which powers both the logic and the memories. It is demonstrated how Xenergic’s SRAM offers best-in class power efficiency, by offering a leakage and access power optimized memory with foundry bitcells. Xenergic’s low-power SRAM enables aggressive voltage scaling of the entire SoC, and the single-rail implementation strategy reduces engineering, integration and area cost. Static power consumption of the entire SoC (processing logic and SRAM) is significantly reduced. The square dependency of the dynamic power on the supply voltage will result in dramatic dynamic power savings. The study shows that Xenergic’s industry leading SRAM technology is a key enabler for highly optimized Tensilica-based systems.
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Updating your Automotive SoC from 16FFC to N7
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