1 : Front-End Power
The majority of gains in low power occur in the early stages of design – the architecture and microarchitecture level. Being able to make effective decisions at that stage requires a combination of data and technology to accurately predict how they will translate into the final product, which traditionally has not been possible. We will give an overview of the Cadence methodology for analyzing and optimizing the design to arrive at the lowest power end product, covering functional verification, high-level synthesis, RTL synthesis, and power estimation/optimization. This session is followed by a series of deep dives into the individual products and technologies involved.
Rob Knoth, Director, Product Marketing, Cadence
2 : Using Genus-iSpatial Flow to address congestion problem and achieve better PPA
"By calling the same engines (GigaPlace/GigaOpt/EarlyClockFlow) of Innovus, Genus-iSpatial can achieve a better physical correlation with Innovus. In Unisoc modem case, comparing with the original synthesis flow, Genus-iSpatial can significantly alleviate the congestion problem."
3 : Signoff in the Era of “More Than Moore”: Challenges and Solutions
Signoff in the era of “more than Moore”, in which major foundries invest heavily in advanced packaging while keep shrinking transistor size, is full of new challenges which mainly come from the increasing design size and system complexity. In addition, signoff TAT is even requested to be shortened to face intense competition. To meet more stringent signoff requirements, Cadence signoff tools keep innovating in the areas of increasing tool capacity, improving tool scalability, enhancing tool integration to shorten the entire digital flow TAT, and enriching system analysis and signoff solutions. In this presentation, many new solutions will be covered such Voltus-XP, Voltus-XM, Cadence Signoff on Cloud, Innovus-PI, Tempus-PI, Tempus-ECO, Voltus-Sigrity 3DIC Signoff Flow and Voltus-Celsius ET Cosim.
Albert Zeng, Cadence
4 : In-design full-flow IR drop avoidance and optimization
In the chip design at advanced node ,due to the increase of the transistor density and the metal resistance, the probability of IR drop violation increases. How to quickly fix these violations has become a difficult point in the signoff stage . The traditional method analyzes and fix the chip's IR drop violation after the place&route, which requires multiple iterations and is not easy to converge. With the help of Cadence's newly introduced In-design full-flow IR drop fixing and avoidance , the author uses IR aware automatic placement, skewClock IR fixing, and local P/G stripe addition, etc., to avoid and fix the possible IR hot-spot during the placement and routing stage,which effectively prevents the occurrence of IR drop violations, improves the efficiency of IR drop hot spot fix, and greatly accelerate the convergence of static voltage drop and dynamic voltage drop..
5 : Voltus IR co-simulation of AI 2.5D chip with multi-die and package
Power integration analysis is more and more important in nm level tech node. This is an AI chip of 12nm using 2.5D to integrate HBM with interposer. And full ASIC design contents 450M instance excluding fillers and near 10B PG nodes. It is a huge and complex simulation work for IR analysis. Besides that, we add interposer design and package model both net-base and pin-base to co-simulation to check IR of full system. Cadence Voltus XP technology provide a fully complete flow and high capacity engine. With Voltus XP and multi-die feature, we do static IR and dynamic IR analyses of mix-mode with both vector-less and vector-base. Advanced features 3D-IC enable multi-die analysis with interposer and package together. Voltus XP technology helps to do parallel computing which accelerates run time to finish dynamic rail simulation in 1 day. Getting benefit by this total solution, we verified the whole chip design IR status and achieved signoff criteria.
6 : Solution for Signoff-Silicon Power/IR Correlation with Voltus and Sigrity
Performance and power are more and more important on advanced node, while they are tradeoff factor.To achieve higher performance, we need calculate power and whole system IR accurately. Our target is to find a reasonable solution for signoff and silicon power/IR drop correlation when the conditions are different. Voltus static power analysis mode with the peak power vector from silicon test patten can get more accurate power range. It's very important for power forecast on early stage. More performance margin can be released for design. Co-analysis flow on Voltus and Sigrity can help to get a good trend prediction on whole system IR drop..