Industry-wide interoperability and reusable verification IP
The Universal Verification Methodology (UVM) is a standard being developed by Accellera for the expressed purpose of fostering universal verification IP (VIP) interoperability. Championed and supported by electronics companies throughout the verification ecosystem, the UVM will increase productivity by eliminating the expensive interfacing that typically slows VIP reuse.
The UVM is based on the Open Verification Methodology (OVM) 2.1.1 release. The early adopter release in May 2010 incorporates some incremental functionality to validate the SourceForge-based development process. The extended functionality becoming available in the pending UVM 1.0 release derives from the combined strengths of the Verification Methodology Manual (VMM), the OVM, and new technology developed by the Accellera VIP Technical Subcommittee. Along with the base-class library (BCL), the UVM provides two important documents: a reference manual for APIs in the UVM and a user guide suggesting how to apply the UVM—both of which originated with the OVM but have been updated to the UVM. Accellera members have tested the UVM on multiple simulators to enable the VIP developed with it to run universally. The UVM BCL and documentation, along with additional contributions, blogs, and forums, are available immediately for download from www.uvmworld.org.
As with OVM, the UVM power to scale comes from the UVM verification component (UVC) which is an abstraction of the stimulus and monitoring needed to verify a design component, interface or protocols. It is architected for multiple verification languages and defined by a set of classes and methods in the UVM library. Since all UVCs follow this same structure—containing the sequence, monitor, and driver for a specific design interface—the entire verification ecosystem will easily understand how to reuse the UVCs they receive. UVM UVCs can also be integrated hierarchically and controlled by virtual sequences, enabling the verification environment to smoothly scale from block to system.
Cadence has also contributed to UVM World an open-source UVM Reference Flow. This reference flow is a complete RISC-based SoC design plus a set of UVM verification components (UVCs), allowing users to learn about the UVM and execute their UVM testbenches. The UVM Reference Flow is a subset of the Incisive Verification Kit, which provides powerful hands-on workshops, labs, and videos for comprehensive user understanding. And just like with the OVM, the real productivity gains with the UVM are when it is implemented in a metric-driven verification flow, which leverages the power of constrained-random testing within a functional coverage environment with automation to ensure productivity. When the abstraction provided by the UVM used within the verification intent and fast convergence demonstrated in the UVM Reference Flow, project teams are empowered with the best UVM approach for achieving Silicon Realization.
- Delivers an open, unified class library and methodology for interoperable VIP
- Eliminates need for interoperability among multiple verification libraries
- Based on a base-class library proven in thousands of projects
- Provides built-in automation and testbench capabilities
- Supports module-to-system and project-to-project reuse
- Incorporates the collective verification knowledge of Accellera members
- Runs on any simulator supporting the IEEE 1800 standard
- Enables multi-language plug-and-play VIP
- Includes a methodology user guide and reference documentation
- Integrates with the proven metric-driven verification flow