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Digital Design and Signoff

Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

PRODUCT CATEGORIES

  • Logic Equivalence Checking
  • SoC Implementation and Floorplanning
  • Functional ECO
  • Low-Power Validation
  • Synthesis
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  • Constraints and CDC Signoff
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FEATURED PRODUCTS

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Custom IC / Analog / RF Design

Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.

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  • RF / Microwave Solutions

FEATURED PRODUCTS

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Verification

Offering a full verification flow to our customers and partners that delivers the highest verification throughput in the industry

PRODUCT CATEGORIES

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FEATURED PRODUCTS

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IP

An open IP platform for you to customize your app-driven SoC design.

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IC Package Design and Analysis

Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.

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System Analysis

Cadence® system analysis solutions provide highly accurate electromagnetic extraction and simulation analysis to ensure your system works under wide-ranging operating conditions.

PRODUCT CATEGORIES

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FEATURED PRODUCTS

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Embedded Software

PCB Design and Analysis

Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.

PRODUCT CATEGORIES

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  • Products
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Genus Synthesis Solution
          • Conformal Smart LEC
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Virtuoso RF Solution
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus IC Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Emulation and Prototyping
          • Formal and Static Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • JasperGold Formal Verification Platform
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • Interface IP
          • Denali Memory IP
          • Tensilica Processor IP
          • Analog IP
          • System / Peripherals IP
          • Verification IP
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • System Analysis
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Omnis
          • Sigrity Advanced SI
          • Sigrity Advanced PI
          • RESOURCES
          • System Analysis Resources Hub
          • AWR Free Trial
      • Embedded Software
      • PCB Design and Analysis
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • RESOURCES
          • What's New in Allegro
          • What's New in Sigrity
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
    • PERVASIVE INTELLIGENCE
      • AI / Machine Learning
      • AI IP Portfolio
    • CADENCE CLOUD
    • VIEW ALL PRODUCTS
  • Solutions
      • Industries
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • Technologies
        • 3D-IC Design
        • Advanced Node
        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • Industries
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • Technologies
        • 3D-IC Design
        • Advanced Node
        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • Industries
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • Technologies
        • 3D-IC Design
        • Advanced Node
        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
  • Support
      • Support
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        • Languages and Methodologies
        • Digital Design and Signoff
        • IC Package
        • PCB Design
        • System Design and Verification
        • Tensilica Processor IP
      • Support
        • Support Process
        • Online Support
        • Software Downloads
        • Computing Platform Support
        • Customer Support Contacts
        • Technical Forums
      • Training
        • Custom IC / Analog / RF Design
        • Languages and Methodologies
        • Digital Design and Signoff
        • IC Package
        • PCB Design
        • System Design and Verification
        • Tensilica Processor IP
      • Support
        • Support Process
        • Online Support
        • Software Downloads
        • Computing Platform Support
        • Customer Support Contacts
        • Technical Forums
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        • Custom IC / Analog / RF Design
        • Languages and Methodologies
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Standards
and Languages

Provide continuous support for a variety of design and
verification languages and implementation standards

One language can’t solve all design and verification problems. Different teams use different languages to take advantage of the unique features each one provides. As a leader of open standards, Cadence® is dedicated to providing continuous support for a variety of design and verification languages and implementation standards.

You can find overviews of the key industry standards and languages that Cadence supports below:

  • Verilog
  • VHDL
  • SystemVerilog
  • Property Specific Language (PSL)
  • SystemC
  • Encryption

We also support these languages and standards:

  • e Verification Language
  • ECSM library format
  • Open Verification Methodology (OVM)
  • Universal Verification Methodology (UVM)

For implementation tools, Cadence supports LEF, DEF, GDSII, SDF, and SPEF. To date, Cadence has donated and made accessible to the industry more than a dozen major proprietary languages, formats, API specifications, and reference implementations, including Verilog, VHDL, SystemC, GDSII, SDF, LEF, DEF, and ECSM.

To ensure unified standards for advanced design and verification, and to improve the process of turning specifications into fully implemented standards, Cadence is an active participant in the Accellera and IEEE standards committees.

Verilog

Verilog is the incumbent de facto and IEEE standard (IEEE 1364-2001) for RTL design. Used widely since the 1980s and supported by all major EDA vendors, Verilog is the basis for most logic synthesis tools. The language provides good support for ASIC design and verification of simple and moderately complex chips. While it has limitations for more complex designs, Verilog remains the language of choice for a broad cross-section of today’s designers who are not involved in leading-edge projects or who use it as an implementation language in a multi-language design and verification flow.

VHDL

VHDL (IEEE 1076) enjoys a similar position to Verilog in terms of its scope and application to synthesizable design. Its appeal is rooted in its precise semantics and higher level abstraction. VHDL does continue to evolve with the latest update standardized in 2008 (IEEE 1076-2008).

SystemVerilog

SystemVerilog is an IEEE 1800 standard that expands on base Verilog language by adding convenience and abstraction extensions for design, assertions, and verification. The new design features enable more efficient design coding through virtual interfaces, generators, enumerated types, and more. The testbench features enable object-oriented programming using dynamic types, randomization, constraints, and more, so that SystemVerilog can be applied to complex verification tasks.

Property Specific Language (PSL)

PSL (IEEE 1850) supports Verilog, VHDL, and SystemC. It includes multiple abstraction layers for assertion types ranging from low-level boolean and temporal to higher level modeling and verification. PSL does continue to evolve; the latest update is the IEEE 1850-2010 standard.

SystemC

SystemC (IEEE 1666) is ideal for transaction-level modeling and high-performance reference modeling. SystemC can also be synthesized; there’s a technical committee of the Accellera Systems Initiative working on a standard language subset for synthesis. Testbenches for SystemC can be written in SystemC, but many product teams choose UVM and/or e, enabling reuse of the tests at the next lower level of abstraction with Verilog and VHDL.

Encryption

With more design teams distributed across different regions, there’s an increased need to exchange IP within a single company and among companies in a design chain. The IEEE P1735 Recommended Practice for Encryption and Management of Electronic Design IP seeks to standardize the safe interchange of IP. The practice leverages public key encryption that allows multiple tools in the design chain, from multiple vendors, to operate on the IP.

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