Length : 3 days
This course covers modeling, simulation and analysis of parallel bus systems, and serial link systems using Sigrity™ SystemSI™.
After completing this course, you will be able to:
- Build a block-level topologies of parallel bus systems (PBSs) in the System SI-PBA II tool and serial link systems (SLSs) in the SystemSI-SLA II tool.
- Assign IBIS models to the functional blocks of the PBSs and SLSs.
- Generate W-Element transmission line model to represent pre-routed parallel bus or serial link interfaces.
- Connect blocks of PBSs and SLSs, using the model connection protocol (MCP).
- Set analysis options, including channel simulation options before simulating these PBSs and SLSs.
- Set voltage and current probe points in PBSs and SLSs.
- Set various types of sweeping parameters.
- Run simulations and sweep simulations.
- Generate simulation based reports with tables and waveforms.
- View tables, 2D plots, Eye Diagrams, BER Eye plots, Bathtub plot, impulse and ramp responses of channel, etc.
- Analyze simulation-based results, waveforms and tables to evaluate the power and signal integrity performance of the PBSs and SLSs.
- Modify the PBSs by replacing the S-parameters model of the parallel bus interface by its broadband circuit model, by adding another memory block(s), by replacing IBIS models of the controller and memory blocks, etc.
- Modify SLSs by adding AMI models or by adding IBIS-AMI models to transmitter and receiver blocks, adding Via models, generated by the built-in Via Wizard etc.
- Use the built-in serial link system template for crosstalk analysis for exploring signal degradation of the primary serial link channel due to other coupled serial links.
- Run simulation of the modified PBSs and SLSs and generate simulation based results.
- Compare power and signal integrity performance of the modified PBSs and SLSs, based on the waveforms, timing parameters in the tables of the generated reports.
Software Used in This Course
SystemSI Parallel Bus Analysis II (SystemSI-PBA II) SIGRITY2017, SystemSI Serial Link Analysis II (SystemSI-SLA II)
- Electrical engineers and PCB designers involved with design-oriented modeling, simulation and analysis of pre-routed and post-routed high-speed parallel bussystems (DDR3/DDR4), and serial link systems (SerDes).
You must have an understanding of power and signal integrity issues of high-speed DDR3/DDR4 parallel bus systems and serial link system, and an understanding of transmission lines and S-parameters.
Sigrity PowerSI for Model Generation and Analysis