Length : 1 day(s)
Course Description
In this course, you launch and generate an Abstract in Standalone mode, create pins by Mapping Text Labels to Pins, create Well Pins in the Abstract Generator, create the Pwell Pin with No Overlapping Pwell Shape, preserve the Local Blockages in the design, calculate Antenna Values in the design, create various Blockage types in the abstract generator (Cover, Detailed, Shrink), use the various Blockage options of “Cut Same” and “Cut Below” under the Blockage tab in Abstract Step, group Power Geometries in the LEF File, run the Standalone/Batch mode of Abstract and LEF File Generation in Tcl mode, run the Standalone/Batch mode of Abstract and LEF File Generation in SKILL® mode with Hook, launch and generate the abstract using the Integrated Abstract Generator, abstract Pcells with the Dynamic Abstract Generator.
Learning Objectives
After completing this course, you will be able to:
- Set up and run Virtuoso Abstract Generator in Standalone Mode
- Analyze the Pins step
- Analyze the Extract step
- Analyze the Abstract step
- Set up and run Virtuoso Abstract Generator in Tcl Mode
- Set up and run Virtuoso Abstract Generator in SKILL Mode with Hook
- Set up and run Integrated Abstract Generator
- Use Dynamic Abstract Generation for VSR
Software Used in This Course
- Virtuoso® Layout Suite
- Encounter® Digital Implementation System
Software Release(s)
IC 6.1.7, EDI 142
Modules in this Course
- Running Virtuoso Abstract Generator in Standalone Mode
- Exploring the Pins Step
- Exploring the Extract Step
- Exploring the Abstract Step
- Running Virtuoso Abstract Generator in Tcl Mode
- Running Virtuoso Abstract Generator in SKILL Mode with Hook
- The Integrated Abstract Generator
- Dynamic Abstract Generation for VSR
- Launching and Generating the Abstract in Standalone Mode (Optional)
Audience
- Layout Design Engineers
- Layout CAD Managers
- IC Designers
- Analog/Mixed-Signal IC Designers
- Analog IC Designers
- Custom Circuit Designers
- Chip Designers
Prerequisites
You must have:
- Experience with layout design
- Knowledge of schematic symbols and MOS devices
- A basic knowledge of UNIX/Linux
